Not sure if all the focus is not missing something here. When do we get to looking at how Vref is affecting the sound?
Let me rephrase "Vref" to DAC Power Supply.
It means it is impacted by the analogue signal and any logic noise that "get's past" decoupling.
How about the effects of how the doubled clock is being generated?
I think this was discussed, using a local crystal clock and synchronising the source to it was
@bohrok2610 's solution, something I agreed with.
In order to retain a simple "stand alone" DAC without worrying about cIock domains and synchronisation I suggested a Si5317 DPLL clock cleaner, which can be set to 60Hz bandwidth and offers sub-ps RMS jitter above a few 100Hz. One might want to play with the hardware settings to see if it possible to trick the IC into lower bandwidth while retaining low jitter.
As bonus, we can use Si5317 as clock multiplier to (say) 4 X input BCK to allow RTZ with 75% duty cycle as opposed to 50%.
I'll be those things have as much or more effect on the sound as does all the focus on little switching glitches.
Possibly.
Also, Cestrian already built an output stage board with OPA1632 and says the mushy sound is now gone.
So it suggests to me (circumstantial evidence) that the problem is attributable to a combination of the OPA2210's common emitter output stage and intermodulation of switching noise at this point. So OPA1632 or my suggestion of "Birt" compound with a hybrid adding a low noise OPA with a differential CFB OPA outpput would look very likely good solutions.
Then once we fix all that other stuff, maybe we will hear an audible difference from rerouting shift register bypass currents? Probably we would, at least IME it seems rather likely.
Ditto.
So far bohrok2610's measurements seem to indicate that the filter is the performance bottleneck, at least for low-level distortion due to intermodulation between out-of-band signals, but assuming that that will be fixed
My concern is that at least in theory we should not have this. FIR lowpass and inherent RC filtering with 3uS turnover (~53kHz) should keep supersonic problems at arms length.
If additional LC filtering helps, we need to consider that we have a fidelity impairment risk upfront in our DAC structure, which is unexpected actualised with certain types of analogue stages.
There is a good chance that an SN74ACT16374A would outperform two SN74LV574A's, though I can't be sure about that.
16374 Bus Latches come in many different logic families.
On the positive side, the supply and ground pin-out is definitely better, and looking at the symmetry of the pin-out, chances are that the whole chip is laid out symmetrically.
Knowing human nature this is not certainty, but likely.
On the other side, the chip is somewhat slower, and no one knows which has least 1/f noise.
I suspect 1/f noise is family dependent.
I haven't seen an explicit skew specification in the TI datasheet, by the way.
There are extended application notes (I seem to remember sharing some here and others with you? Maybe not) that go into this in detail for different logic families. Fascinating reading heavy on grap[hs..
When you drive SN74ACT16374A inputs from a dirty 3.3 V domain, the high inputs will draw an overlap current from the 5 V reference that depends on the momentary voltage at the dirty 3.3 V.
You mean through the P-Channel device's Ciss? It is probably worth slowing the edges here to minimise this feedthrough.
I don't see the advantage of separating the shift register from the output registers, except maybe that the load on the last flip-flop will then better match that of its colleagues. The data clocked into the output registers will be the same, no matter whether you use them only as output registers or also as a shift register.
Correct. Signal is not really affected as such.
HOWEVER, the current in the 5V DAC Supply will differ.
If we slow edges of the data lines to guard against feedthrough and have a complementary layout and signals we can expect substantially less "spikey" current on the reference.
There is just less swicherigerdiroo going on on that chip. As said, a chip with dual supply domains for input and output we can improve the situation a little more.
What is more, done right, the DAC will latch the data on the "idle" cycle of all the other logic and even the logic on the input's would have settled any ground/supply bounce by the time we do the DAC update. It should deal with jitter produced LIM and minimise it to least possible. By the time we get ground/supply bounce from updating the DAC storage register the clock edge will have already been registered and the DAC update has begun, while all other circuitry has already settled.
Regarding return to high impedance (or return to off) rather than return to zero, I think it will be difficult to keep intersymbol interference under control with such a scheme.
Remains to be seen.
With a nonideal virtual ground or no virtual ground at all, the voltage the output would settle to in its high-impedance phase would depend on more previous bits, presumably making things worse.
But our output always depends on previous bit's. The question is, will the averaged errors even out, the way RTZ allows for uneven rise & fall time.
1. I reckon
@bohrok2610 uses the TVSOP package (?) whereas for convenience I chose to use the TSSOP package in all three layouts. Although the package inductance differences between the pins of these two packages are not "huge" this could be an explanation for the THD differences between the layouts.
Could be, trying a 16 Bit part may be a "hack". Personally I stick to TSSOP simply from a supply chain view.
4.
@bohrok2610 appears to use a smaller size decoupling capacitor which may/might also imply a lower inductance of this capacitor (and possibly a better decoupling of the VCC pin noise).
In systems with full ground and power planes usually the determining factor for bypassing are the pins, PCB Pads and via's, the planes have enough capacitance to swamp out any sensible bypass Cap's inductance.
@ThorstenL : Interesting information about PCB stackup, thanks for mentioning them. One thought here: Since the identical potential and impedance of the VCC and GND planes depend on the even - and efficient - decoupling at all frequencies between these planes - i.e. a fully linear decoupling capacitor arrangement between these planes - will you not see a frequency-dependent & thus uneven trace impedance on the VCC and GND sides of a signal trace being placed between a VCC & GND plane?
You seem to miss the point. The concept's of ground are fiction.
If we look at an Inverter, the reference point for the N-Channel is Vss (aka "GND") and when it pulls an input and a strip-line low the current return path is via the Vss power plane (aka Ground Plane). The reference point for the P-Channel is Vcc (aka "PWR") and when it pulls an input and a strip-line high the current return path is via the Vcc pin.
So depending on the PCB structure this current either returns via a bypass capacitor and the ground plane and another bypass capacitor (as we do not have a contiguous Power plane surrounding the signal line) or via our Vcc power plane.
It is all about current loops.
Incidentally, if there is enough space, the following stack-up allows something near 6-layer performance on 4 layers.
Top -> Components + GND
Int1 -> Signal 1 / Power 2
Int2 -> Signal 2 / Power 1
Bot -> (Components +) GND
It requires a lot of layout discipline, as we need a "as uninterrupted as possible" power plane on a layer that also handles routing. It is doable, however it is often challenging.
That why my default now is:
Top -> Components + GND
Int1 -> Signal 1
Int2 -> Power 1
Int3 -> Power 2
Int4 -> Signal 2
Bot -> (Components +) GND
Or:
Top -> Components + GND
Int1 -> Signal 1 / Analog
Int2 -> Power 1 / Analog Power +
Int3 -> Power 2 / Analog Power -
Int4 -> Signal 2 / Analog
Bot -> (Components +) GND
Or:
Top -> Components + GND
Int1 -> Signal 1 / Signal 3 / Analog
Int2 -> Power 1 / Power 3 / Analog Power +
Int3 -> Power 2 / Power 4 / Analog Power -
Int4 -> Signal 2 / Signal 4 / Analog
Bot -> (Components +) GND
In this last case Power 1 may be 1.2V core for FPGA, XMOS etc. or split up into 1.2/1.8/2.5V sections per IC depending on Vcc Core demands. Signal 1 would be all signal lines operating at core level and/or uncritical signals.
Power 3 on the same layer might be the DAC Vcc and Signal 3 would be "DAC internal" or again "uncritical".
Power 2 would be the common I/O Power (often 3.3V) and Signal 2 all critical signal wiring referencing to Power 2.
Power 4 could be for example the clock section conceivably with drivers that isolate the Power 2 domain clock tree from the DAC in the Power 4 domain.
Layout would divide into DAC sections L/R, clock in-between the DAC's and finally a large "dirty digital" section.
Going 8 layer is desirable for designs with a complex and timing critical clock tree, especially where devices driven by the clock are in a different clock domain.
By dedicating one layer (say top) to key clocks and ground-fill and the next layer to ground we create a situation where EMC emissions are increased compared to buried lines, but we have highly consistent behaviour as there will no gap's in power planes between power domains. That gives
Top -> Components + CLK (+ GND-Fill)
Int1 -> GND
Int2 -> Signal 1 / Signal 3 / Analog
Int3 -> Power 1 / Power 3 / Analog Power +
Int4 -> Power 2 / Power 4 / Analog Power -
Int5 -> Signal 2 / Signal 4 / Analog
Int6 -> GND
Bot -> (Components +) low speed routing (+ GND-Fill)
Having a solid ground under each high speed IC is still desirable in this setup.
Thor