Unstable buffer

Status
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.
Voltwide had a good observation. I repeated his test and found:

1. disabling the cascode helped phase margin a little, but it was still kind of iffy.
2. Adding 100 pF from collector to base of Q1 gets pretty good phase margin.

Of course, if the sim and reality agree...that remains to be seen!
the sim tells you that the circuit responds to capacitance in that location.
Armed with that knowledge you can now test the real amplifier and try different values of capacitor in that location. Try from 0pF to 220pF in steps of 10pF. Or maybe a small air spaced variable cap.
 
Any changes with capacitance between Q2 base and Q4 collector?
Q5 base capacitance about 20pF to gnd shows instability.
No positive effect.

Did you try this, R10 C8 ?

This one does the trick, at last. It is perhaps a little brutal though.
I'll have to check the impact on performances, and see if it is possible to use less aggressive values.
 
Disabled Account
Joined 2010
Generally, a buffer is intended for high impedance sources - consequently the simulation should reflect this. I suggest .step simulations with a variety of signal source series resistors.
To achieve wide bandwidth over a range of source impedance it is imho mandatory to drive the input bjt with constant collector-emitter voltage, i.e. in a cascode configuration.
 
As I feared, the fix significantly degrades the 100KHz linearity.
It isn't simply the low pass effect of the filter though: in sim, just inserting the 150 ohm without capacitor already account for half of the degradation.
It probably harms the cascode effect in some way, but at the moment I do not see clearly by which mechanism.
I may try a different filter: a well damped second order would cut more sharply the higher frequencies, leave intact the frequencies of interest and reduce the series resistance. It could also cause all hell to break loose once again....
Anyway, even the watered down version remains usable, that is certainly better than nothing.
Generally, a buffer is intended for high impedance sources - consequently the simulation should reflect this. I suggest .step simulations with a variety of signal source series resistors.
To achieve wide bandwidth over a range of source impedance it is imho mandatory to drive the input bjt with constant collector-emitter voltage, i.e. in a cascode configuration.
It does have a very high input impedance for a wide range of frequencies, that is not a problem, and the input transistor also benefits from the cascode, there is little that can be improved there.
 
As I more or less expected, inserting an inductor anywhere near the filter has apocalyptic effects.

Fortunately, I have found an alternative way of compensating the cascode, which is not only stable in sim and reality, but actually manages to improve the linearity.

With this hack, the largest harmonic product of 100KHz is the third, at ~16ppb. The bandwidth is perfectly flat up to >10MHz, thus it begins to look good. That is in sim, of course, but that is the first step.

The trick was to use a Miller compensation instead of shunt. I also had to fix minor issues, like a low level instability under some conditions: a 68 ohm damping on the 1µH was sufficient to tame it.

Now that the circuit basically functions, I will be able to make more detailed checks.

Here is the (provisionally) final circuit:
 

Attachments

  • UltraBuffer4.png
    UltraBuffer4.png
    83.1 KB · Views: 205
Member
Joined 2002
Paid Member
I played a bit with the circuit

Anyway, I do not like overall fb with multiple pole compensation at all.

It's wisdom. I am reminded of a professional class ( by MEAD ) that I took as a green engineer. An IC amplifier design expert from TI basically said, "just don't design circuits with more than two poles, whatever you think you are gaining from it you pay for in unreliability." But of course this is ASIC design where you have to design for +/- 30% component variation and -40C to 150C junction temperatures. So in a custom discrete design perhaps you can get away with it if you can tweak out the unpredictable parasitics.

And later as a more seasoned designer I had some intractable problems with a 3 stage high speed precision voltage error amp that just wouldn't be stable in reality, until we disabled remote sensing, despite good behavior in simulation and the best efforts of three experienced analog designers. So I am a big proponent of KISS design philosophy.

That said, as much as I want to make some suggestions to simplify this circuit's open loop transfer function, I am so intrigued by its design topology that I'll hold off on that for now... even though the inductor in the emitter of that last stage makes me so queasy.

But, this circuit evidently is trying to meet some really difficult and extreme performance criteria. Elvee, can you describe the operation and design method and/or point to some references for this topology? Can you concisely specify the requirements in a deliberate way so that we can properly consider alternatives that might be more robust against unanticipated parasitics but still meet the requirements?
 
Last edited:
These simplifications do not look advantageous: they spare a few inexpensive passives at the cost of ruining the performances and stability:
Remember, the original circuit achieves ~30ppb THD with 10Vpp ouput, and is stable: it has been tried and tested.
I am almost certain (certain in fact) that forgoing the stability components will lead to instabilities in reality, even if they don't show in sim.

This circuit is going to be used for instrumentation purposes, and will not process directly baseband audio. For this application, objective performance is more important than taste.
 

Attachments

  • UltraB.png
    UltraB.png
    134.7 KB · Views: 295
Disabled Account
Joined 2010
My simplifications do not aim to save unexpensive compents, but define a circuit that has a managable frequency response ("KISS")
And yes, my "taste" is based on the fact that multiple voltage gain stages with multiple gain poles are very difficult to stabilize.
Empirical compensating by trial and error is one way - designing a predictable circuit is another. To prove the stability in reality, many tests are necessary:
-various input source resistors
-square signals of various amplitude
-various output load resistors
-various output load capacitances
After all I can only trust a circuit with a completely understood loop gain / bode plot behaviour.

As there is no size that fits all, it would be helpfull if you give precise specifications of your goal:
-max signal level
-range of input impedance
-range of output impedance
-bandwith
-linearity
 
The circuit only has one "signal loop", that of the CFP follower.

The other loops, current and voltage are "transverse", or orthogonal, and only have a minor effect on the core behavior of the follower: they can be both disabled, and the circuit will basically continue to operate in the same way, except for tiny details like linearity which are important for me.

Basically, this circuit fits my bill for the time being. It is just the instability that was bugging me. Ideally, when I will have been able to validate my concepts, I would like to have something even better, but first I need to do some work, and also check how well the sim figures translate in reality. At the moment, they are completely unverifiable (and are probably seriously out)
 
I haven't read the whole thread.
But two questions rises up after read post #72:
1) what happens, if you replace Q2 and Q1 (Sziklai Darlington) through a single transistor?
That is what Voltwide tried in sim (#70). In reality, I do not know, and now that the thing is stable, I do not want to experiment further.
2) what happens, if you enhance the idle currents (10mA for Q2, 30mA for Q1 and the associated values for the others)?
The current in Q1 is already ~35mA.
10mA through Q2 would require an excessive bias current for me
 
To be more complete (I am only aware now of some of the comments): this buffer is a building block of a very sensitive (extreme?) distortion-meter (not existing yet, has been in the making for a number of years).

Ideally, it would be <1ppb capable, but this is essentially a "sanity" requirement: in order to resolve 1ppb, its own THD only needs to be one or two order of magnitude worst with the principle used (at this level, only coherent methods of HD extraction are possible, because the noise level is equal or higher than any distortion product).
At the moment, the simulated THD is 30ppb, and the actual THD is certainly much higher, but I will only be able to cross-check the actual level when I have sufficiently progressed. It will take some time, and may never happen in case I am following the wrong route....

Anyway, the buffer circuit itself only has one major feedback path: the two other ones are accessory (but may nevertheless lead to oscillation through higher order couplings with the main path, which seemed to be the case here)

The present circuit works satisfactorily and eventually, when I need even higher performance, I can build on this foundation and use active compensation rather than simple stasis: something like Unigabuf (or Kuartlotron or Dmitri's version of buffer or any comparable correction circuit)
 
Status
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.