Hi Damir,
Thank you for your suggestions. Agree with you about the CCS at the input. Was thinking of using an LED based CCS. Trying to avoid any control loops. Have enough of them already in this design. Which CCS do you like the best?
DC servo is also my favourite option.
Will give the Baker clamps a go. I don't like D3, D4 either but it does give good clipping while being simple but then so are baker clamps.
Gainwire is currently in use attached to a dual AK4399 DAC as a headphone amp. It is lovely. Sony in ear headphones have no right to sound so good.You have done a wonderful job on that design!!
Paul
Regarding the CCS try this type suggested by Sergio: http://www.diyaudio.com/forums/solid-state/260308-gainwire-ngnfb-classb-poweramp-6.html#post4028879
and implemented in this amp http://www.diyaudio.com/forums/solid-state/260308-gainwire-ngnfb-classb-poweramp-11.html#post4045598
I did not try it in real amp yet, but it promises good behavior.
Damir
CCS looks good. Hasn't got any internal feedback which fits the bill. Will simulate and maybe implement in my prototype.
Another question, why have you got a 15pF cap across the input stage in the Gainwire ngnfb class b power amp? Has this input stage topology got stability problems without it?
Paul
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Those are Miller caps for Q15, Q16, and it improved the Loop Gain plot, as IPS has it's own NFB. I don't remember if it was unstable without it, I have to simulate it again. That was just one aberration from non GNFB.
Damir
Ah, thank you, have to have look myself. So much to learn.
One problem I'm having with this amp is that it is difficult to get good PM/GM in the main loop while keeping good performance. This is probably down to the number of stages. eg. Enhanced VAS followed by effectively a 3EF.
The solution I can see for this is to optimise the internal loops such that they are faster and can be run at similar speeds but with better stability. The only problem is that I'm not sure how to go about this and how to approach the optimisation.
Ah, thank you, have to have look myself. So much to learn.
One problem I'm having with this amp is that it is difficult to get good PM/GM in the main loop while keeping good performance. This is probably down to the number of stages. eg. Enhanced VAS followed by effectively a 3EF.
The solution I can see for this is to optimise the internal loops such that they are faster and can be run at similar speeds but with better stability. The only problem is that I'm not sure how to go about this and how to approach the optimisation.
Faster transistors for the HEC loop devices will also increase available bandwidth for the feedback/feedforward loops, depending on layout, better linearity
. There is a problem finding transistors that are very fast and will sustain a large breakdown voltage. Cascode?
Also it is good to include not only a base stopper resistor with these very fast transistors but also a small collector stopper as well to prevent RF ringing. This will help the global loop gain BW if you are intent on including the HEC stage within the global loop. Included within the DC servo loop, certainly but I wonder if it must be in the loop that sets the limits on the VAS? Maybe the VAS load could be the "global" loop (voltage divider resistors || Miller) and the HEC would be just along for the ride?Another Update
Been doing some more development. Added CCS to front end and have been playing with the compensation. The Baker clamps have yet to be implemented though.
Have attached the stability plots for the main loop (Blue)and the VAS loop (Green). I think they look ok but would appreciate a second opinion.
It still plays music and I can't see any oscillation on the scope.
CBS240 - I like your ideas. They make sense to me but at present they may be a little advanced. The HEC will be devloped once I'm happy with the front end.
Paul
Been doing some more development. Added CCS to front end and have been playing with the compensation. The Baker clamps have yet to be implemented though.
Have attached the stability plots for the main loop (Blue)and the VAS loop (Green). I think they look ok but would appreciate a second opinion.
It still plays music and I can't see any oscillation on the scope.
CBS240 - I like your ideas. They make sense to me but at present they may be a little advanced. The HEC will be devloped once I'm happy with the front end.
Paul
Attachments
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MOSFET gate clamps and HEC:
I've seen in varous schematics now that these clamps are still places at the gates of the FETs. I don't think that's the right location any more. You see, on a short-circuit fault, all the HEC transistors (Q9, Q13, Q19) will try to fully conduct. When you then look at the zenerdiode array, they are the sole load to the + rail. These diodes are blown instantly, taking the MOSFETs with them a fraction after.
I prefer to attach the array at the inputs of the HEC: The bases of Q9 and Q10. The zener voltage needs to be higher than the zener reference voltage feeding the HEC (D1/D9) to allow the HEC some room around the output reference, though low enough, that when you subtract all the BE junctions after the clamp all the way up to the gates of the MOSFETs, you get your intended clamp value. I'm using 15V clamps, which leaves me some 12V after the HEC as the maximum gate voltage.
If you now shortcircuit the output, the clamps will shunt the VAS current and they can sustain that slightly better than the output current of a emitter follower.
Ofcourse you still have to limit your maximum VAS current, but if you do, then you have an actual sustainable short-circuit protection up till the fuses in the OPS power leads do their job. But no, the zeners may NOT go before the fuse goes.
I've seen in varous schematics now that these clamps are still places at the gates of the FETs. I don't think that's the right location any more. You see, on a short-circuit fault, all the HEC transistors (Q9, Q13, Q19) will try to fully conduct. When you then look at the zenerdiode array, they are the sole load to the + rail. These diodes are blown instantly, taking the MOSFETs with them a fraction after.
I prefer to attach the array at the inputs of the HEC: The bases of Q9 and Q10. The zener voltage needs to be higher than the zener reference voltage feeding the HEC (D1/D9) to allow the HEC some room around the output reference, though low enough, that when you subtract all the BE junctions after the clamp all the way up to the gates of the MOSFETs, you get your intended clamp value. I'm using 15V clamps, which leaves me some 12V after the HEC as the maximum gate voltage.
If you now shortcircuit the output, the clamps will shunt the VAS current and they can sustain that slightly better than the output current of a emitter follower.
Ofcourse you still have to limit your maximum VAS current, but if you do, then you have an actual sustainable short-circuit protection up till the fuses in the OPS power leads do their job. But no, the zeners may NOT go before the fuse goes.
Magicbox,
Good point. I had noticed in your thread that you had done it that way. Saves components as well especially if you have multiple pairs of output devices.
Another option would be to use class A drivers. The current would then be limited by the CCSs. In the past have made a working HEC using the folded driver circuit in Bob Cordell's book.
Paul
Good point. I had noticed in your thread that you had done it that way. Saves components as well especially if you have multiple pairs of output devices.
Another option would be to use class A drivers. The current would then be limited by the CCSs. In the past have made a working HEC using the folded driver circuit in Bob Cordell's book.
Paul
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Have thought some more about magics idea about using the zeners at the HEC input. I don't like the idea of the exposed MOSFET gates. I like the idea of having an array there too but of higher voltage. Then would need to carefully choose the VAS current limits. Or use as cascoded VAS with current limit resistors. Seeems an elegant way to do it.
I'm sorta with you. I was thinking of adding the 'positive' clamp to the HEC and add a 'negative' clamp directly at the gate rail of the FET, and vice versa for the other side of the amp.
But still, in a short circuit fault condition those will blow if the driver currents aren't limited. Current sources in their collector leads may be the 'ultimate' solution to keep the diodes alive and functioning. But those CCSes should be set at a higher current than programmed for the driver, and a transistor with a capable Vce should be used; when in fault condition, this transistor will take the full rail voltage at the given CCS current (minus clamp voltage). But alas, it adds yet another bit of complexity, although a sensible one if you want to be on the safe side for short circuits.
But still, in a short circuit fault condition those will blow if the driver currents aren't limited. Current sources in their collector leads may be the 'ultimate' solution to keep the diodes alive and functioning. But those CCSes should be set at a higher current than programmed for the driver, and a transistor with a capable Vce should be used; when in fault condition, this transistor will take the full rail voltage at the given CCS current (minus clamp voltage). But alas, it adds yet another bit of complexity, although a sensible one if you want to be on the safe side for short circuits.
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I have found that it is important that the HEC stage is stable. Taking it out of the global loop showed me that mine was not unconditionally stable and I had to readjust the local compensation. For now I still prefer to place it inside the loop, but I am not convinced it is necessary.
As for a clamp, I find this to be an important addition in preventing excess gate charge. Once the mosfet is Vds saturated as in clipping, Vgs increases quite a bit in order to squeeze any more conduction from the mosfet because of the action of the HEC circuit. All of this excess gate charge must be removed by the driver stage in order to turn the mosfet off as the output leaves clipping. Notice also the internal mosfet capacities also increase significantly at Vds saturation. This could lead to rail sticking and cross conduction, shoot trough.
In the output stage of my mosfet stereo amp I used a clamp on the base of the driver stage. The pre-driver before it is current limited, so the diodes won't see enough current to fail them. This clamp should not activate until the output mosfet is fully Vds saturated. Here is schematic of that circuit. There is a new version of this project in the works, but there is only minor changes to the output stage. I still intend to use the planer stripe fets as I find them to be especially rugged.Attachments
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I can follow that. I've always been wondering how to limit the driver current of an HEC OPS. One solution may be to have bootstrapped drivers. Then the diodes have to last long enough to collapse the bootstrap? You could have a bootrapped HEC input stage instead.
Knew the driver current through the diodes needed limiting just never thought of some of the ideas I have just read.
This all leads to have proper OPS current limiting. Always like to have some protection for the OPS devices.
Sounds like an interesting experiment to take the HEC out of the global feedback.
Seems like a waste not to have the HEC inside the loop but can see the advantages of taking it out.
As for a clamp, I find this to be an important addition in preventing excess gate charge. Once the mosfet is Vds saturated as in clipping, Vgs increases quite a bit in order to squeeze any more conduction from the mosfet because of the action of the HEC circuit. All of this excess gate charge must be removed by the driver stage in order to turn the mosfet off as the output leaves clipping. Notice also the internal mosfet capacities also increase significantly at Vds saturation. This could lead to rail sticking and cross conduction, shoot trough.
This is a neat solution to the problem.
That sort of added complexity is good. Thank you for sharing your idea.Impressed at the compensation cap values. That looks to be a very fast HEC!
Smaller currents in the error circuit indicate larger Z. So for the same roll off frequencies the cap value is smaller.
Tight layout helps too. The last pictures are top and bottom of both output stage circuits, right & left. The transistors in the red boxes are Trench type mosfets, rail switches. The devices in the yellow boxes are the error transistors, in thermal contact with the drain pins. I still use this amp almost daily, listening now in fact. In the waveforms, you can see the differences between the gate drive and output signals. Mosfet bias is around 50mA. Third picture is the 'error' signal referenced to the output, representing the change in Vgs vs conductance. Note the significant slope around the zero crossing.
Tight layout helps too. The last pictures are top and bottom of both output stage circuits, right & left. The transistors in the red boxes are Trench type mosfets, rail switches.
The devices in the yellow boxes are the error transistors, in thermal contact with the drain pins. I still use this amp almost daily, listening now in fact. In the waveforms, you can see the differences between the gate drive and output signals. Mosfet bias is around 50mA. Third picture is the 'error' signal referenced to the output, representing the change in Vgs vs conductance. Note the significant slope around the zero crossing.Attachments
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CBS240 - Thank you for those screen shots of the real amp. A couple of those are going to be very useful as I'm now trying to get my head round analysing the HEC in detail. The loopgain plots so far, at first look bad. Then you actually think about what you are seeing and it makes sense.
If you meant my crazy creation... Can only provide figures from LTSpice, I'm afraid.
All simmed with 8R resistive load.
Clipping = +/-23V
20kHz +/-21V = 0.001046%
1kHz +/-21V = 0.000037%
20khz +/-3V = 0.000359%
1kHz +/- 3V = 0.000016%
Reality will be very different, I know.
Paul
P.S. THD isn't the priority with this amp, stability is.
If you meant my crazy creation... Can only provide figures from LTSpice, I'm afraid.
All simmed with 8R resistive load.
Clipping = +/-23V
20kHz +/-21V = 0.001046%
1kHz +/-21V = 0.000037%
20khz +/-3V = 0.000359%
1kHz +/- 3V = 0.000016%
Reality will be very different, I know.
Paul
P.S. THD isn't the priority with this amp, stability is.
At present, yes, although it may well get reduced as it probably is unnecessarily high. It's only really 45mA as 20mA goes into the HEC.
Yes, but it makes ~17W to dissipate in each MJE15032C & MJE15033C and 4W in the BC550 & 560.
Oh Lord !
Laterals don't ask a lot more than 6mA/device from drivers. Any reason why HEC need so much current ?
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