I have a question, that must have a simple answer, but has been driving me crazy. I am simulating a basic 3-stage BJT amplifier, the circuit you will recognize from Bob Cordell's book on Designing audio Power Amplifiers. I have attached the schematic. When I simulate as a simple block diagram, everything works as I would expect. When I simulate the circuit, there is a dependence of the VAS current and emitter degeneration resistor (R5) that manifests itself as an offset in Vout. Seems like that offset should be driven to zero my the nature of the closed loop, but it does not seem to be the case? Any thoughts would be very appreciated.
If current of Q14 and 15 are not balanced their will be DC offset at the output.
You can use a current mirror to improve this balance.
Or in this simplified case R4 usually would need to be within 5% to 1% value
So try anything from 887, 909, 931, 953, 976 ohms to get DC offset lower.
R5 can be lowered to 18 to 27ohms to also adjust offset at the output.
Regardless the current of Q14 and 15 need to equal.
And wouldn't mess around with anything else till that is achieved
with R4 value.
Simplified designs such as this will tend to tolerate 30 to 45mV DC on the output.
By using 1% resistor value for R4 assume 8 to 15mV
The input is not AC coupled with a capacitor or loaded to ground.
So expect even more DC offset. And feedback network R6 would also be AC coupled.
Dont know if your sim allows temperature to be set on the devices.
So 22 to 27c is good place to start and technically the thermal tracking temp of
Q8 will never be the same as the outputs. It will be slightly colder.
You can use a current mirror to improve this balance.
Or in this simplified case R4 usually would need to be within 5% to 1% value
So try anything from 887, 909, 931, 953, 976 ohms to get DC offset lower.
R5 can be lowered to 18 to 27ohms to also adjust offset at the output.
Regardless the current of Q14 and 15 need to equal.
And wouldn't mess around with anything else till that is achieved
with R4 value.
Simplified designs such as this will tend to tolerate 30 to 45mV DC on the output.
By using 1% resistor value for R4 assume 8 to 15mV
The input is not AC coupled with a capacitor or loaded to ground.
So expect even more DC offset. And feedback network R6 would also be AC coupled.
Dont know if your sim allows temperature to be set on the devices.
So 22 to 27c is good place to start and technically the thermal tracking temp of
Q8 will never be the same as the outputs. It will be slightly colder.
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There really is nothing to be surprised about. Circuit balance in a real-world rendition will never be exact, device tolerances make sure of that.
The OLG isn't infinite so output offset won't be zero. Now, if your simulation's Vos is really large that will be a red flag, indicating that something really is amiss. But you haven't said what output offset you're seeing so who knows?
The OLG isn't infinite so output offset won't be zero. Now, if your simulation's Vos is really large that will be a red flag, indicating that something really is amiss. But you haven't said what output offset you're seeing so who knows?
Since it is not AC coupled and the second stage current is likely high, with high emitter resistor value.
My wild guess is 50 to 65 mV
My wild guess is 50 to 65 mV
220 x2 is a lot of LPT degen and will cause a lot of offset for a given amount of LTP current imbalance. A current mirror will largely eliminate LPT current imbalance. The current in R5 will be 0.65/62 or about 10mA so the value of R5 sets the base voltage of Q4 and there for the current in R4 and the LPT imbalance.
Too much playing with simulations can make anyone too picky. I know I'm guilty of excessive circuit tweaking.....
A single resistor in place of R12+R13 provides cross-coupling which improves cross-over and reduces shoot-through current. 300p for C1 is probably excessive and leads to TIM. THD is better with a Darlington VAS but may require reducing the gain with LTP degen and larger C1. Degen on the VAS protects it from excessive current on clipping but otherwise is a dubious choice and causes a bit of phase reversal on clipping.
Thank you all so much for these thoughtful and well thought out comments. This problem was driving me crazy. I could see it was the load on the LTP, but I just never picked up on the current imbalance of the LTP causing this offset. Through lowering R4 and adjusting the value of the emitter degeneration resister of the VAS I was able to bring the DC offset of Vout to about 9mV. Next step will be to add a current mirror to the LTP, which I should have done all along and adding the ac coupling ti the inout and feedback path, which was going to be my next step.
I made some changes to the circuit, but still have a few questions about Vout offset voltage with in input applied. I added a current mirror to the LTP and also added a darlington configuration to the VAS stage. The circuit below has a very well match current in the LTP with 1.063mA in both collectors. The offset Vout is coming in at 141mV in my simulation. I can increase the load on the LTP by lowering the value of the degeneration resistor R19 in the VAS to 150 ohms and that drops my Vout offset to just over 1mV, but the LTP collector currents are now 1.077mA and 1.049mA. An offset voltage of 141 mV is not acceptable, but not sure what the best way of fixing this issue. I know I need to add ac coupling and choose a different transistor for Q8 that I can mount on the heatsink, but this offset issue is driving me crazy. Any thought again would be greatly appreciated.
