Whilst looking at some typical architectures for 2-stage active/passive RIAA preamps, I noticed that if the stage order [shelving gain (3180us/318us pole/zero) --> LPF (75us pole) --> gain] is chosen, the final gain stage can be configured as a 2nd order state variable filter (SVF), with the high-pass output used to implement a rumble filter, and the 75us pole incorporated into the SVF input resistor (R1 in the picture below).
This allows the rumble filter to be implemented without adding an additional stage (typically a Sallen-Key HPF) after the RIAA equalisation, and as the DC offset at the HP output of the SVF is controlled (equal to the input ofset of the SVF second opamp), no output DC-blocking capacitor is required.
State Variable Filter. The first opamp becomes the second stage of the RIAA preamplifier:
The complete circuit:
The main features are:
- The first stage implements the RIAA 3180us/318us pole/zero pair using the values originally proposed by Baxandall, which give impressive accuracy with common values. DC gain is 40dB falling to 20dB above 500Hz, so with an opamp such as the OPA2134 (characteristics shown below), the closed loop bandwidth can be seen to be >200kHz with an excess loop gain of ~30dB at 20kHz, giving good distortion attenuation.
- The RIAA 75us pole is incorporated into the input resistor of the SVF by splitting R1 into two sections, giving the exact time constant using common values. This can be done as its 2122Hz LP corner frequency will be more than 2 orders of magnitude above the <20Hz corner frequency of the rumble filter, with the inverting input of the opamp tending to a virtual earth at frequencies above this.
With a fixed gain above the HF cut-on of 19dB, again the excess loop gain is ~30dB at 20kHz.
- All resistors are E12 (if we slightly cheat and form R1 above from a pair of 1k5 in parallel - R4 above is already split into a series pair of 1k5), and capacitors E3.
Total gain is 39.2dB @ 1kHz, with a rumble filter HP corner frequency of 17.3Hz and Q = 0.71 for a Butterworth response.
Simulated frequency response (with inverse RIAA compensated input):
This has been prototyped, installed in re-purposed tuner chassis:
Measured frequency response (inverse RIAA compensated in ARTA):
Measured output noise, input shorted with 100R (measurement noise floor shown in yellow-ish):
Step response, 10mV step, and overload case, 50mV step:
1kHz sine, 6v RMS output, and overload case:
Stripboard PCB layout of one of the prototype channels:
This allows the rumble filter to be implemented without adding an additional stage (typically a Sallen-Key HPF) after the RIAA equalisation, and as the DC offset at the HP output of the SVF is controlled (equal to the input ofset of the SVF second opamp), no output DC-blocking capacitor is required.
State Variable Filter. The first opamp becomes the second stage of the RIAA preamplifier:
The complete circuit:
The main features are:
- The first stage implements the RIAA 3180us/318us pole/zero pair using the values originally proposed by Baxandall, which give impressive accuracy with common values. DC gain is 40dB falling to 20dB above 500Hz, so with an opamp such as the OPA2134 (characteristics shown below), the closed loop bandwidth can be seen to be >200kHz with an excess loop gain of ~30dB at 20kHz, giving good distortion attenuation.
- The RIAA 75us pole is incorporated into the input resistor of the SVF by splitting R1 into two sections, giving the exact time constant using common values. This can be done as its 2122Hz LP corner frequency will be more than 2 orders of magnitude above the <20Hz corner frequency of the rumble filter, with the inverting input of the opamp tending to a virtual earth at frequencies above this.
With a fixed gain above the HF cut-on of 19dB, again the excess loop gain is ~30dB at 20kHz.
- All resistors are E12 (if we slightly cheat and form R1 above from a pair of 1k5 in parallel - R4 above is already split into a series pair of 1k5), and capacitors E3.
Total gain is 39.2dB @ 1kHz, with a rumble filter HP corner frequency of 17.3Hz and Q = 0.71 for a Butterworth response.
Simulated frequency response (with inverse RIAA compensated input):
This has been prototyped, installed in re-purposed tuner chassis:
Measured frequency response (inverse RIAA compensated in ARTA):
Measured output noise, input shorted with 100R (measurement noise floor shown in yellow-ish):
Step response, 10mV step, and overload case, 50mV step:
1kHz sine, 6v RMS output, and overload case:
Stripboard PCB layout of one of the prototype channels:
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You can get a free extra LF HP pole by restoring Baxandall's C1, at a higher value to suit your desired cutoff frequency.
Surely it would be better to put the SVF before the RIAA, so you don't have to amplify LF so much? More headroom that way.
Surely it would be better to put the SVF before the RIAA, so you don't have to amplify LF so much? More headroom that way.
Hi ejp, interesting comments.
Yes indeed (the 10uF shown gives a 21Hz HP so close to what would be needed to match the 17Hz chosen here), and then modify the HP SVF Q to 1.0 to give the correct 3rd-order response. I decided against using C1 as a HPF to avoid any signal-dependant distortion as described here on hifisonix.com, he typically uses 10x the value in the C1 position for DC blocking to avoid the issue, but here the DC offset at the output is taken care of by the SVF, so C1 is not included. The SVF uses lower-value film capacitors in the integrators so should not suffer the same effect.
Yes more LF headroom in the first (and second) stage, but headroom here is I think not limiting. As configured, the transfer function along the signal path is shown in the left-hand graph, with the output having the least headroom. Re-ordering the stages as suggested gives the right-hand graph - there is certainly more headroom earlier in the path, but again the output has the least. You are of course amplifying the LF by the same amount overall, but the higher 1st stage LF gain as configured should potentially be beneficial for overall noise. (There is the additional practical detail that the SVF input is not high input impedance so not suitable as the input stage).
I hadn't come across this implementation before, but it seemed a practical solution - no high value capacitors, HPF with no 'extra' stage (but 2 more opamps of course), DC servo, fast settling, accurate RIAA. Just another variant to add in to the mix!
Yes indeed (the 10uF shown gives a 21Hz HP so close to what would be needed to match the 17Hz chosen here), and then modify the HP SVF Q to 1.0 to give the correct 3rd-order response. I decided against using C1 as a HPF to avoid any signal-dependant distortion as described here on hifisonix.com, he typically uses 10x the value in the C1 position for DC blocking to avoid the issue, but here the DC offset at the output is taken care of by the SVF, so C1 is not included. The SVF uses lower-value film capacitors in the integrators so should not suffer the same effect.
Yes more LF headroom in the first (and second) stage, but headroom here is I think not limiting. As configured, the transfer function along the signal path is shown in the left-hand graph, with the output having the least headroom. Re-ordering the stages as suggested gives the right-hand graph - there is certainly more headroom earlier in the path, but again the output has the least. You are of course amplifying the LF by the same amount overall, but the higher 1st stage LF gain as configured should potentially be beneficial for overall noise. (There is the additional practical detail that the SVF input is not high input impedance so not suitable as the input stage).
I hadn't come across this implementation before, but it seemed a practical solution - no high value capacitors, HPF with no 'extra' stage (but 2 more opamps of course), DC servo, fast settling, accurate RIAA. Just another variant to add in to the mix!
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