Conventionally, the VAS could be enhanced by adding emitter-follower at the front, shown as below. However, there is a drawback that the VAS transistor would overload and burn up in some situation.
I do know adding some protection components would solve the overload situation almost perfectly.
Anyway, I found another way to construct the VAS without worrying about overloading, shown as below.
Instead of buffering the input stage(IPS) with a emitter follower, you could buffer the IPS with a JFET source follower. Note that the JFET above is a P channel JFET. The voltage at the Gate is higher than the voltage at the base of Q6. It forms a source follower in a folded way. Thus, there is no fear that the Q6 would be overloaded.
Thanks to the high input impedance at the Gate. The amp has very high open loop gain at low frequency.
Loop gain:
I do know adding some protection components would solve the overload situation almost perfectly.
Anyway, I found another way to construct the VAS without worrying about overloading, shown as below.
Instead of buffering the input stage(IPS) with a emitter follower, you could buffer the IPS with a JFET source follower. Note that the JFET above is a P channel JFET. The voltage at the Gate is higher than the voltage at the base of Q6. It forms a source follower in a folded way. Thus, there is no fear that the Q6 would be overloaded.
Thanks to the high input impedance at the Gate. The amp has very high open loop gain at low frequency.
Loop gain:
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It appears that mirror transistors Q13 and Q14 will operate at substantially different Vce's and thus, through the Early effect, have different collector currents. Q13 and Q14 currents are unfortunately not mirrored 1-to-1. Perhaps some fixup shenanigans could help, maybe going as far as a 4 transistor full Wilson mirror circuit.
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Isn't the offset due to the worst-case mismatch between two pairs of discrete transistors big enough to make that negligible? If it is really a problem, you could use a matching P-channel JFET source follower as "helper" for the current mirror.
That's why I always keep the degeneration resistors in the current mirror. Those 100 Ohm resistors could make the output impedance (of the current mirror) higher than that without them. Less early effect into play.
The worst case mismatch between discrete NPNs has been a factor of ~ 40 smaller than the worst case mismatch between discrete P-channel JFETs, every time I've measured them. But if you allow matching P-channel JFETs then surely you'll allow matching NPNs too.
And I suspect you'd apply a lot more than (4 * kT/q) millivolts across the emitter degeneration resistors too.
Just using the same JFET type and drain current should suffice. The offset is roughly a factor of VA/(kT/q) >> 40 times less sensitive to mismatch between the JFETs than between the bipolar transistors.
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Another candidate, a simple mosfet VAS. Please ignore Vce mismatch from the current mirror at this point.
mosfet has less gm comparing to bjt. However, if the input stage is loaded with current mirror, the less gm doesn't matter at all.
mosfet has less gm comparing to bjt. However, if the input stage is loaded with current mirror, the less gm doesn't matter at all.
I did a similar thing in the Hornet front end card for the Ship Of Theseus amplifier. Its first stage is an (unusual, mixed-sex) differential amplifier, driving a cascoded current source load (Q3, U1). Thanks to the cascode, there needed to be quite a large voltage drop across the CCS load in order to keep the whole thing in constant current mode and away from the "knee". And, voila, an enhancement mode MOSFET (Q6) provided exactly that. Because its Vgs_threshold voltage was so large (2.5V), the voltage across the current source load was (Vbe_Q8 + MOS_threshold) = 0.65+2.5 = 3.15 volts, which proved to be way more than adequate. Worked great in the simulator, worked great on the bench, sounded great in the listening room. And yes, a diff amp with cascoded current source load, driving the gate of a MOSFET (Zin = infinity), does indeed provide enormous amounts of gain. { gm * (Rload // Zin_VAS) } is huge when Rload and Zin_VAS are both huge.
BTW note the push pull complementary source follower output stage (Q9 & Q10) with no source resistors.
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BTW note the push pull complementary source follower output stage (Q9 & Q10) with no source resistors.
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The right-half-plane zero gets closer to the origin with a lower transconductance, but your plots show it is still far enough.