Amplifiers - Feedback/Loopgain stability simulated vs. real world
In many threads here I have expressed my doubts on accuracy of amplifier circuit simulations, especially in two points – very low harmonic distortions <0.001% and feedback (loopgain) unconditional stability. Based on my long, decades lasting experience in designing, building and testing power amplifiers I am declaring that transistor models available with freely distributed simulators like LTspice and others are not accurate enough to simulate neither very low levels of harmonic distortions, nor stability issues with complex load at frequencies >1MHz. I am going to prove my statements on the examples of two real world amplifier samples. And this will be also related to methods of frequency compensation of feedback amplifiers, based on Bode plots loopgain simulations.
Two amplifier samples will be analyzed, one with an old-school dominant-pole compensation, the other with more sophisticated TPC compensation, that allows for more loopgain at higher frequencies, thus lower harmonic distortion at higher frequencies. The amplifiers will be analyzed not only for distortion, but also for stability with complex load and this stability will be compared to assumptions derived from loopgain simulations.
1. The amplifier with the dominant-pole compensation
The amplifier sample has been described here in the thread
https://www.diyaudio.com/community/...er-and-my-diy-mods-schematics-gerbers.406947/
Loopgain simulation says that with a resistor load (4.7ohm) the phase margin at the point where the loopgain amplitude plot crosses 0dB, at 3.75MHz, is about 80°, which is enough for stable operation. The feedback factor (loopgain) at 20kHz is 41dB, which is the factor available for harmonic distortion reduction of this feedback amplifier, at 20kHz. At =<1kHz, the loopgain is 58dB.
Now, when 47nF capacitor is added in parallel with 4R7 resistor, the loopgain amplitude plot crosses 0dB at 2.45MHz and the phase margin is now a mere 14°, so the amplifier should be close to instability.
Let's investigate the real amplifier sample, with a 10kHz square wave as an input signal, and both discussed loads.
Response into 4.7ohm resistor
The response is nicely aperiodic, with no signs of instability. Exactly according to loopgain simulation.
Response into 4.7ohm//47nF
47nF capacitor was added in parallel with the 4R7 resistor, however the square response remained unaffected. This is not in conformance with the simulated loopgain, which would suggest at least heavy ringing, with the simulated phase margin of only 14°.
The amplifier is stable (in the real world) for wide range of capacitances, covering at least 0 – 100nF. First signs of compromised stability we can see with the 150nF capacitor // 4R7:
So, for this amplifier sample with dominant-pole compensation, the simulation was pesismistic compared to the real world results. Something does not fit, models?
2. The amplifier with TPC compensation
The amplifier sample has been described in the thread
https://www.diyaudio.com/community/threads/sab-class-ab-2x50w-4ohm-amplifier-with-smps.386169/
Loopgain simulation says that with a resistor load (4.7ohm) the phase margin at the point where the loopgain amplitude plot crosses 0dB, at 0.95MHz, is about 50°, which might be enough for stable operation. The feedback factor (loopgain) at 20kHz is 57dB, which is the factor available for harmonic distortion reduction of this feedback amplifier, at 20kHz. At =<1kHz, the loopgain is very high 93dB. Brown line in the graph would be a comparison to a dominant-pole compensation with the same unity gain frequency.
Now, when 47nF capacitor is added in parallel with 4R7 resistor, the loopgain amplitude plot crosses 0dB at almost same point near 0.95MHz and the phase margin is now a mere 30°, not much less than without the capacitor, and the amplifier should be still stable.
Another plot is with 15nF capacitor, and we can see that the phase margin is now 43°, definitely enough for the amplifier to be stable, at least in the simulation!
But how about the real world sample?? Alas, the amplifier's response oscillates with 4R7//15nF!
And increasing the capacitor to 47nF makes oscillations with much higher amplitude and the amplifier has suddenly blown the T5A fuse in the +rail of the power supply. But, due to very robust MJL21194/93 output pair, it has survived.
I inserted the 0.4uH output coil behind the amplifier's output ad now it was able to drive 4R7//33nF load with slight signs of oscillations only.
Test bench, load and output coil
So, with the more sophisticated compensation scheme, we have got this improvement in THD+N vs. frequency at the expense of much worse amplifier stability, though the simulations did not suggest the stability worsening.
It is up to you to make a choice, if you prefer some inaudible improvement in THD+N, or an unconditional amplifier stability. And remember, do not forget to use the output coil with feedback amplifiers!
In many threads here I have expressed my doubts on accuracy of amplifier circuit simulations, especially in two points – very low harmonic distortions <0.001% and feedback (loopgain) unconditional stability. Based on my long, decades lasting experience in designing, building and testing power amplifiers I am declaring that transistor models available with freely distributed simulators like LTspice and others are not accurate enough to simulate neither very low levels of harmonic distortions, nor stability issues with complex load at frequencies >1MHz. I am going to prove my statements on the examples of two real world amplifier samples. And this will be also related to methods of frequency compensation of feedback amplifiers, based on Bode plots loopgain simulations.
Two amplifier samples will be analyzed, one with an old-school dominant-pole compensation, the other with more sophisticated TPC compensation, that allows for more loopgain at higher frequencies, thus lower harmonic distortion at higher frequencies. The amplifiers will be analyzed not only for distortion, but also for stability with complex load and this stability will be compared to assumptions derived from loopgain simulations.
1. The amplifier with the dominant-pole compensation
The amplifier sample has been described here in the thread
https://www.diyaudio.com/community/...er-and-my-diy-mods-schematics-gerbers.406947/
Loopgain simulation says that with a resistor load (4.7ohm) the phase margin at the point where the loopgain amplitude plot crosses 0dB, at 3.75MHz, is about 80°, which is enough for stable operation. The feedback factor (loopgain) at 20kHz is 41dB, which is the factor available for harmonic distortion reduction of this feedback amplifier, at 20kHz. At =<1kHz, the loopgain is 58dB.
Now, when 47nF capacitor is added in parallel with 4R7 resistor, the loopgain amplitude plot crosses 0dB at 2.45MHz and the phase margin is now a mere 14°, so the amplifier should be close to instability.
Let's investigate the real amplifier sample, with a 10kHz square wave as an input signal, and both discussed loads.
Response into 4.7ohm resistor
The response is nicely aperiodic, with no signs of instability. Exactly according to loopgain simulation.
Response into 4.7ohm//47nF
47nF capacitor was added in parallel with the 4R7 resistor, however the square response remained unaffected. This is not in conformance with the simulated loopgain, which would suggest at least heavy ringing, with the simulated phase margin of only 14°.
The amplifier is stable (in the real world) for wide range of capacitances, covering at least 0 – 100nF. First signs of compromised stability we can see with the 150nF capacitor // 4R7:
So, for this amplifier sample with dominant-pole compensation, the simulation was pesismistic compared to the real world results. Something does not fit, models?
2. The amplifier with TPC compensation
The amplifier sample has been described in the thread
https://www.diyaudio.com/community/threads/sab-class-ab-2x50w-4ohm-amplifier-with-smps.386169/
Loopgain simulation says that with a resistor load (4.7ohm) the phase margin at the point where the loopgain amplitude plot crosses 0dB, at 0.95MHz, is about 50°, which might be enough for stable operation. The feedback factor (loopgain) at 20kHz is 57dB, which is the factor available for harmonic distortion reduction of this feedback amplifier, at 20kHz. At =<1kHz, the loopgain is very high 93dB. Brown line in the graph would be a comparison to a dominant-pole compensation with the same unity gain frequency.
Now, when 47nF capacitor is added in parallel with 4R7 resistor, the loopgain amplitude plot crosses 0dB at almost same point near 0.95MHz and the phase margin is now a mere 30°, not much less than without the capacitor, and the amplifier should be still stable.
Another plot is with 15nF capacitor, and we can see that the phase margin is now 43°, definitely enough for the amplifier to be stable, at least in the simulation!
But how about the real world sample?? Alas, the amplifier's response oscillates with 4R7//15nF!
And increasing the capacitor to 47nF makes oscillations with much higher amplitude and the amplifier has suddenly blown the T5A fuse in the +rail of the power supply. But, due to very robust MJL21194/93 output pair, it has survived.
I inserted the 0.4uH output coil behind the amplifier's output ad now it was able to drive 4R7//33nF load with slight signs of oscillations only.
Test bench, load and output coil
So, with the more sophisticated compensation scheme, we have got this improvement in THD+N vs. frequency at the expense of much worse amplifier stability, though the simulations did not suggest the stability worsening.
It is up to you to make a choice, if you prefer some inaudible improvement in THD+N, or an unconditional amplifier stability. And remember, do not forget to use the output coil with feedback amplifiers!
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PMA, I don't think TPC (or TMC) is less stable than MC if you have optimised it for operation in that mode ie if the designer thinks it has signs of instability, perhaps they have been too aggressive (optimistic) in setting the ULGF and in the output inductor value.
I test all my amplifiers with a 2-3V pk-pk square wave and a range of load capacitances from .5 nF all the way up to 2.2uF and circa 3 kHz although I do test at higher frequencies.
The ULGF has to be selected with the output stage configuration in mind IMV.
YMMV 🙂
I test all my amplifiers with a 2-3V pk-pk square wave and a range of load capacitances from .5 nF all the way up to 2.2uF and circa 3 kHz although I do test at higher frequencies.
The ULGF has to be selected with the output stage configuration in mind IMV.
YMMV 🙂
Indeed simulation models for active devices are never perfect...
In simulations differential pairs are always perfectly matched for one thing, unlike real life. And real devices are non-linear but ac-analysis in Spice assumes ac-linearity I think. And often the high frequency poles and zeroes are over-simplified, and internal distortions not even emulated (many opamp models have no common-mode distortion for example).
But that doesn't mean simulation results aren't extremely useful as an initial part of designing and proving a circuit - much time saved, and with power amps probably quite a few components saved from accidental frying - a crowded breadboard makes it very easy to have a few accidents that release the smoke.
And process variation in real components means that even if you built a version that behaves, it doesn't necessarily guarantee the next copy of it behaves.
In simulations differential pairs are always perfectly matched for one thing, unlike real life. And real devices are non-linear but ac-analysis in Spice assumes ac-linearity I think. And often the high frequency poles and zeroes are over-simplified, and internal distortions not even emulated (many opamp models have no common-mode distortion for example).
But that doesn't mean simulation results aren't extremely useful as an initial part of designing and proving a circuit - much time saved, and with power amps probably quite a few components saved from accidental frying - a crowded breadboard makes it very easy to have a few accidents that release the smoke.
And process variation in real components means that even if you built a version that behaves, it doesn't necessarily guarantee the next copy of it behaves.
Every single amplifier is finicky about compensation. You either get it right, or you don't. There are plenty of amplifiers - and one very recent example on this wensite - where no consideration for loop stability is given - even in standard Miller comp designs.
The rules for ascertaining the compensation components are very well understood no matter how you comp and amp. Problems arise when designers push the stability limits to chase 1ppm simulation distortion targets.
I don't think the sim models ultimately determine whether simulated response is going to work or not for loop gain analysis. After all, phase and gain can easily be worked out by hand and you will get a pretty good result - I am talking about standard linear audio amplifiers here. The arrival of sustained beta output devices with fT's of 30 MHz have made the dreaded OPS pole less of a challenge than was the case with the 2955/3055 devices. We should keep in mind that parasitic oscillation, as opposed to loop instability, is a separate issue, and in those cases, I'd agree that the device models will often not provide accurate answers because the HF models don't exist, or are hopelessly inaccurate. I had a case where transistor (2N5551 IIRC) oscillated at 180MHz because I had not used a base stopper, and some may recall the kx-Amp (now superseded by the kx2-Amp) had HF oscillation at 20-40 MHz because I used too high an emitter load resistor on the beta helper transistor. These types of problems are difficult to model.
Here is the link to one of my parasitic oscillation problems - luckily I documented it!
https://hifisonix.com/technical/cascode-amplifier-oscillation/
Here is the link to one of my parasitic oscillation problems - luckily I documented it!
https://hifisonix.com/technical/cascode-amplifier-oscillation/
Kudos for comparing simulation and measurement. 
A small-signal analysis cannot produce accurate results for a class AB output stage because the assumption that the signal is small compared to the bias is not true. The load capacitor lowering the frequency of the pole at the output is not being accurately modeled.
I agree that an output inductor cures that problem.
I design feedback very conservatively. I use one-pole compensation and moderate loop gain. I have no idea where the second pole may be (and it depends on output loading without an inductor).
Ed
A small-signal analysis cannot produce accurate results for a class AB output stage because the assumption that the signal is small compared to the bias is not true. The load capacitor lowering the frequency of the pole at the output is not being accurately modeled.
I agree that an output inductor cures that problem.
I design feedback very conservatively. I use one-pole compensation and moderate loop gain. I have no idea where the second pole may be (and it depends on output loading without an inductor).
Ed
I also observed that loop-gain simulation does not correlate well to the actual build of the amplifier. Like EdGr wrote, this likely has to do with the small signal nature of the AC simulation.
Parasitic oscillation like Bonsai mentioned can be spotted in simulation if some real world effects like PCB inductance and capacitance are modeled. Adding some nH of inductance to the simulation here and there revealed tendency for such instability quite often.
Even if the global loop is compensated in a very conservative way, the amplifier still may not be stable. I once decreased UGLF to ~500kHz and it was still not stable. The root cause was that some circuit blocks were showing some gain peaking in the higher frequency region. This is very difficult to spot in a simulation of the whole amplifier and futile to cure with the global loop compensation. In order to spot such issues, take apart the amplifier into smaller chunks like the LTP, currrent sources, current mirrors, gain stages, buffers and so on and investigate each on their own, both in AC and transient response. You may be surprised how weird some circuit blocks can behave. Once each block is optimized, put them together again and see whether they (still) play together nicely. This method has helped me a lot and in the end I was able to increase UGLF.
Parasitic oscillation like Bonsai mentioned can be spotted in simulation if some real world effects like PCB inductance and capacitance are modeled. Adding some nH of inductance to the simulation here and there revealed tendency for such instability quite often.
Even if the global loop is compensated in a very conservative way, the amplifier still may not be stable. I once decreased UGLF to ~500kHz and it was still not stable. The root cause was that some circuit blocks were showing some gain peaking in the higher frequency region. This is very difficult to spot in a simulation of the whole amplifier and futile to cure with the global loop compensation. In order to spot such issues, take apart the amplifier into smaller chunks like the LTP, currrent sources, current mirrors, gain stages, buffers and so on and investigate each on their own, both in AC and transient response. You may be surprised how weird some circuit blocks can behave. Once each block is optimized, put them together again and see whether they (still) play together nicely. This method has helped me a lot and in the end I was able to increase UGLF.
I agree. And, the more complicated is the amplifier structure in order to minimize harmonic distortion to meaningless low level, the worse and uneven is large signal dynamic non-linearity and the step response shape grossly depends on output amplitude. Much more effort is then needed to assure unconditional stability to complex load. And, testing amplifiers into resistor load only is completely insufficient.Kudos for comparing simulation and measurement.
A small-signal analysis cannot produce accurate results for a class AB output stage because the assumption that the signal is small compared to the bias is not true. The load capacitor lowering the frequency of the pole at the output is not being accurately modeled.
I agree that an output inductor cures that problem.
I design feedback very conservatively. I use one-pole compensation and moderate loop gain. I have no idea where the second pole may be (and it depends on output loading without an inductor).
Ed
Short of measuring each individual component and creating unique models for each part, to create a robust simulation requires stochastic methods where the parameters of the individual transistors in the simulation are varied in a random way within the expected manufacturing variation for each transistor. The same would need to be done for each resistor and capacitor. All the parts not on the schematic need to be included as well, ie. the inductance, resistance and capacitance and coupling of each PCB trace and wire in the build. Automated testing of several thousand builds of the amplifier simulation with different component combinations would sort out the design for manufacturability. So accurate simulation of corner conditions of an amplifier are possible, but it's a lot of effort and a bit outside of the DIY space. If the simulation is built using perfect parts it won't match any given built with part values varying all over the place. As others have stated, the linearized small signal behavior will also be different than the transient simulation that operates with the full non-linear models of the parts.
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While presented analysis and conclusions are excellent, it must be pointed out that response into 150 nF/4.7 Ω, as seen above, is very likely not sign of approaching low phase margin, rather LCR resonant response on fast enough stimulus. There is typical amplitude fall like in a resonant circuit with low Q.
I’ll try to elaborate.
First let’s check response of very fast power amplifier with low dV/dt signal. Capacitor is connected, as is in OP example, with test leads (120 cm total wire length) and internal amplifier wiring is only 30 cm total (both wires). Signal rise time is 3 us into 47 nF||4.5 Ω. We can see that there is practically clean response.
Next is the same load but with 10 times faster rise time, so high dV/dt. Now, there is a considerable “oscillation” at the top of square wave signal. Sign of approaching instability point? Not at all. Amplifier is rock stable.
Test leads inductance + internal amplifier inductance, capacitor and resistive load form a resonant circuit, which with values 360 nH (3 nH per wire cm), 150 nF and 4.5 Ω, has resonant frequency of 685 kHz. Magnified response looks about right.
Proof that this is a LCR resonance.
Capacitor direct across binding posts, with only 90 nH of internal wiring inductance should form resonant circuit at 1370 kHz. Magnified response again looks about right.
Those examples turn exactly the same for small or large signal analysis.
This is also an explanation for what else, except RF filtering, is low pass filter at the amp input good for. It limits input signal speed and may keep it well below frequency of low phase margin caused by capacitive load.
I’ll try to elaborate.
First let’s check response of very fast power amplifier with low dV/dt signal. Capacitor is connected, as is in OP example, with test leads (120 cm total wire length) and internal amplifier wiring is only 30 cm total (both wires). Signal rise time is 3 us into 47 nF||4.5 Ω. We can see that there is practically clean response.
Next is the same load but with 10 times faster rise time, so high dV/dt. Now, there is a considerable “oscillation” at the top of square wave signal. Sign of approaching instability point? Not at all. Amplifier is rock stable.
Test leads inductance + internal amplifier inductance, capacitor and resistive load form a resonant circuit, which with values 360 nH (3 nH per wire cm), 150 nF and 4.5 Ω, has resonant frequency of 685 kHz. Magnified response looks about right.
Proof that this is a LCR resonance.
Capacitor direct across binding posts, with only 90 nH of internal wiring inductance should form resonant circuit at 1370 kHz. Magnified response again looks about right.
Those examples turn exactly the same for small or large signal analysis.
This is also an explanation for what else, except RF filtering, is low pass filter at the amp input good for. It limits input signal speed and may keep it well below frequency of low phase margin caused by capacitive load.
That's too low in my honest opinion. I want for my amplifiers to be able to give full scale output square wave swing.
I know that many commercial amplifiers would have big troubles with such test and I have had bad experience when testing Cello Encore this way.
My PA4 amplifier:
You can always do a power square wave test (see the nx—Amp write up for a scope shot of 70 V pk-pk 100 kHz into 8 ohms).
I have seen quite a few cases on my designs in development where there were small anomalies at 2-3 V pk that were not visible on near full output voltage swing.
(As a general note, a high power square wave test should not be at clipping level - I saw one posted up on the forum a few months ago)
I have seen quite a few cases on my designs in development where there were small anomalies at 2-3 V pk that were not visible on near full output voltage swing.
(As a general note, a high power square wave test should not be at clipping level - I saw one posted up on the forum a few months ago)
The whole idea behind pole splitting aka Miller compensation is that you move the VAS pole and the OPS poles apart and thereby remove loop instability. If you take an uncompensated amp and plot the loop gain, you get a pole at a few kHz and then a pole at a few hundred kHz caused by the output devices which are usually the slowest in an amp. When you apply Miller comp, the first pole (VAS) goes down in frequency to just a few Hz or a few 10’s of Hz and the OPS pole moves up. If you do it correctly, the pole is pushed way beyond the selected ULGF (1 - 3 MHz). There are other HF poles usually up at 30 MHz or more, but these would be 10’s of dB below the ULGF.
If you comp the amp correctly and you still get HF oscillation, there is a very good chance it’s parasitic and that’s a different problem to solve. Loop stability oscillation is normally below 1 MHz and parasitic oscillation above 4 or 5 MHz.
There’s a very good write up about this here:- https://hifisonix.com/wp-content/uploads/2010/10/James-E-Solomon-Opamp-Tutorial.pdf (see page 326 - unfortunately Solomon uses a Nyquist plot to explain the process; a Bode plot makes it much clearer).
If you comp the amp correctly and you still get HF oscillation, there is a very good chance it’s parasitic and that’s a different problem to solve. Loop stability oscillation is normally below 1 MHz and parasitic oscillation above 4 or 5 MHz.
There’s a very good write up about this here:- https://hifisonix.com/wp-content/uploads/2010/10/James-E-Solomon-Opamp-Tutorial.pdf (see page 326 - unfortunately Solomon uses a Nyquist plot to explain the process; a Bode plot makes it much clearer).
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The amp output always resonates with the cable inductance and capacitance - there’s some info here
https://hifisonix.com/wp-content/uploads/2014/11/Output-L_1.pdf
Thats why stability testing is done into a resistive load initially (should be no overshoot on a fast rise time square wave). after that, load capacitance can be adde. You can straightforward calculate the ringing frequency from the output L and the load capacitance.
https://hifisonix.com/wp-content/uploads/2014/11/Output-L_1.pdf
Thats why stability testing is done into a resistive load initially (should be no overshoot on a fast rise time square wave). after that, load capacitance can be adde. You can straightforward calculate the ringing frequency from the output L and the load capacitance.
My latest amplifier has a tendency to oscillate in the ~100kHz to ~200kHz region. This is rather low amplitude, but sustained once triggered. I'm using TPC here. Maybe it is just a coincidence, but may this be related to TPC having a closed loop gain peak somewhere in this frequency region? Anybody has similar experience or any ideas? The CLG peaking of TPC is considered a non-issue as far as I know.
Edit: Needless to say, this doesn't show in simulation.
Edit: Needless to say, this doesn't show in simulation.
TPC does have closed loop peaking - I measured about 1-2 dB IIRC and you can take steps to mitigate it, but I don’t think you can say that is a cause for instability unless you check it carefully. You really have to look at the phase gain relationship to get a handle on what the loop is doing, and how the TPC loop itself is behaving. So there are two loops to look at - thr global loop, and then the TPC loop. TMC does not show this closed loop peaking behaviour.
You would have to show the loop gain plots to discuss further. What have you set your ULGF to? If you lift the TPC resistor that goes to ground, what happens? Does the oscillation go away? Is this oscillation with a capacitive load or just resistive?
(Might be an idea to open a separate thread in this)
You would have to show the loop gain plots to discuss further. What have you set your ULGF to? If you lift the TPC resistor that goes to ground, what happens? Does the oscillation go away? Is this oscillation with a capacitive load or just resistive?
(Might be an idea to open a separate thread in this)
I'm not sure what is the actual root cause for the instability. I mentioned the issue because I found it a good example for how poorly simulation may correlate to reality and there is more to consider than just loop-gain plots.
Loop-gain in my amp shows plenty of stability. Even at ULGF of 1MHz, phase margin was 90° and gain margin ~10dB. Meanwhile I have ~700kHz ULGF and somewhat similar gain margin, lowered the "aggressiveness" of the TPC effect considerably by increasing the resistor and while it looks super stable on the loop-gain plot, it isn't in reality.
Maybe, probably, I don't know, the instability isn't related to compensation at all.
Agree, discussing this specific example may be a bit off topic.
A general observation I made earlier is that setting ULGF rather high may mask some instability, especially gain peaking of some circuitry within the loop. Loop-gain plot looks nice, but the amp isn't really stable. Lowering ULGF may reveal the gain peak, which may show as poor gain margin, probably like some kind of plateau in the gain, that doesn't decrease as quickly as it should.
Loop-gain in my amp shows plenty of stability. Even at ULGF of 1MHz, phase margin was 90° and gain margin ~10dB. Meanwhile I have ~700kHz ULGF and somewhat similar gain margin, lowered the "aggressiveness" of the TPC effect considerably by increasing the resistor and while it looks super stable on the loop-gain plot, it isn't in reality.
Maybe, probably, I don't know, the instability isn't related to compensation at all.
Agree, discussing this specific example may be a bit off topic.
A general observation I made earlier is that setting ULGF rather high may mask some instability, especially gain peaking of some circuitry within the loop. Loop-gain plot looks nice, but the amp isn't really stable. Lowering ULGF may reveal the gain peak, which may show as poor gain margin, probably like some kind of plateau in the gain, that doesn't decrease as quickly as it should.
I think there may be some other issue there. It’s always a good idea to check the amp with straight Miller comp as a first step. If it’s unstable, then solve that first before moving to higher order comp schemes. I have never had a loop stability issue that was that was not apparent in a sim - parasitic oscillation yes, but not loop stability.
I usually put a jumper in my TMC comp resistor in mybamps - if you remove the jumper, the amp reverts to Miller comp which is great for testing and comparing distortion in the two feedback modes.
I usually put a jumper in my TMC comp resistor in mybamps - if you remove the jumper, the amp reverts to Miller comp which is great for testing and comparing distortion in the two feedback modes.
Transient simulation does not fit as well. It has been my long-lasting experience that simulation is inaccurate when investigating stability and HF non-linearities in deep.
Below the comparison of the amplifier #2 (see my post #1) transient (square) response into 4R7//15nF load, simulated generator SR kept same as in case of real generator. Simulation is stable, the real amp oscillates. It is stable only for Cload <= 3.3nF. Of course an output inductor of 1uH in parallel with some 6R8 is a cure, but the simulation does not tell. Projects that finish with simulated results only are all half-baked, and there are more and more of them at DIY audio. DIY means do it yourself, not sit in the armchair and click on keyboard. However, we can see the trend everywhere. It is easier than to build something.
Simulation amp #2, load 4R7//15nF
Measurement amp #2, load 4R7//15nF
One might ask why am I testing such things like large signal square response. The answer is easy - the amplifier must be designed to survive worst case scenario and to keep speakers safe. One of the scenarios is that someone accidentally pulls out the input RCA cable. RCA connector is infamous for the reason that ground connection is disconnected first and live after that. Similarly when someone inserts RCA when the amp is on. Live RCA contact goes first and the amp, depending on system gnd configurations, may go to full output immediately and worse, often goes to MHz range oscillations. I have already seen several broken amplifiers and burnt speakers exactly under the conditions described. So, amplifier operational safety first, under any conditions. Fighting with harmonic distortion of 0.0001% is just a toy game.
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