You will need to operate it at the ridiculously low Id current of 60µA. These devices are not well suited to these conditions, especially if you intend to use the -C suffix.
You should use a 2N4338 or similar.
You should use a 2N4338 or similar.
I want to get max headroom and linear gain from a BF245 with a B+ of 24VDC, and a load of 200K. I’ve had a look at the data sheet, but can’t determine the sweet spot (drain and source resistor values) for this FET. Can anyone help me?
If you choose a BF245A with a IDS of 2.5mA and place about 12V accross the drain resistor of 4.7K you will get at output impedance of ~4.7Kohm. Then you have to choose the right biaslevel and the right source resistor to the the right degration of gain.a starting point could be a 470Ohm source resistor.
You will need to operate it at the ridiculously low Id current of 60µA. These devices are not well suited to these conditions, especially if you intend to use the -C suffix.
You should use a 2N4338 or similar.
How did you work that out?
Would +15VDC be better for this device?
When biasing them, do you somehow find a load line, then work out an Id , and find Sorce resistor to supply that current? Sorry for the bonehead questions, I dont know how to do it
Look at the following datasheet from NXP, its easier to read.
http://www.nxp.com/acrobat_download/datasheets/BF245A-B-C_2.pdf
If you look at fig 3. you can see the maximum drain current. its 4mA. Below 1mA the VGS/ID transfer curve becomes unlinear.
In Fig 4. you can see that below 5V Uds you enter the ohmic region. So thats you limit regarding output swing.
By choosing an rs of 470Ohm we degenerate the gain to about ~10 with and rd of 4.7k .. But we make the it less dependend on the internal rs and more linear.
So with a 470ohm + 4.7k resistor, 24V supply. a min Uds of 5V the max current is 19V/5170Ohm=3.6mA. This will give you a delta ids of 2.6mA or a delta voltage sving over rd of 4.7K*2.6mA = 12.22Vpp to be linear. Now you have to choose you bias voltage on the gate.... remember that you center ids should be 2.6mA and you slope is 1/rs or 1/470ohm. For this you should use fig.3
It gives you a voltage of 1.22volt subtracted with the vgs of -0.5V at 2.6mA => gives you a bias voltage of 0.72volt on the gate....
Remember lower gain makes it more linear.
Best regards
Sonny
http://www.nxp.com/acrobat_download/datasheets/BF245A-B-C_2.pdf
If you look at fig 3. you can see the maximum drain current. its 4mA. Below 1mA the VGS/ID transfer curve becomes unlinear.
In Fig 4. you can see that below 5V Uds you enter the ohmic region. So thats you limit regarding output swing.
By choosing an rs of 470Ohm we degenerate the gain to about ~10 with and rd of 4.7k .. But we make the it less dependend on the internal rs and more linear.
So with a 470ohm + 4.7k resistor, 24V supply. a min Uds of 5V the max current is 19V/5170Ohm=3.6mA. This will give you a delta ids of 2.6mA or a delta voltage sving over rd of 4.7K*2.6mA = 12.22Vpp to be linear. Now you have to choose you bias voltage on the gate.... remember that you center ids should be 2.6mA and you slope is 1/rs or 1/470ohm. For this you should use fig.3
It gives you a voltage of 1.22volt subtracted with the vgs of -0.5V at 2.6mA => gives you a bias voltage of 0.72volt on the gate....
Remember lower gain makes it more linear.
Best regards
Sonny
Hi Sonny,
Thanks for your reply.
Im trying to get it.
To give me a further example, can you please comment on the baising and conditions of the first gain stage BF245 in the following schematic :
http://www.albertkreuzer.com/pics/el/pre/schem/preamp_sch21.gif
Thanks for your reply.
Im trying to get it.
To give me a further example, can you please comment on the baising and conditions of the first gain stage BF245 in the following schematic :
http://www.albertkreuzer.com/pics/el/pre/schem/preamp_sch21.gif
A drain resistance of 4.7K is a much more sensible proposition. Why do you insist on having 200K?
T1 and T2 is not biased - the idle current is subjected to change in temperaturer and production tolerance... T1 i biased around 0.6mA and T2 at 0.5mA at room temperature. But it rises fast when mounted in i case. T3 is biased correctly but R23 will generate thermal noise as it is a 3.3MOhm resistor. Should have something like 330K and R24 something like 100K
A drain resistance of 4.7K is a much more sensible proposition. Why do you insist on having 200K?
Hi, Ive found out that the the input Z in the following stage can be between 600R and 220K, so it doesnt have to be 200K...If 4.7K drain resistance is more sensible (for what ever reason) I think that will be ok for the following stage....
T1 and T2 is not biased - the idle current is subjected to change in temperaturer and production tolerance... T1 i biased around 0.6mA and T2 at 0.5mA at room temperature. But it rises fast when mounted in i case. T3 is biased correctly but R23 will generate thermal noise as it is a 3.3MOhm resistor. Should have something like 330K and R24 something like 100K
Thanks.
How do I bais if I dont want to use a coupling cap at the input? (because it ruins the tone; I want to connect the gate directly to the pickups in my bass guitar)
You need to read up on it. Go to the library for example... Below i have googled a few links.
http://www.det.mmu.ac.uk/staff/travis/open/subject/64ET1516_E/NOTES/S_JFET____TUT_2p.pdf
http://www-personal.engin.umd.umich.edu/~fmeral/ELECTRONICS II/09%c3-FET Project/JFET_Project.pdf
JFET BIASING TUTORIAL BY W7ZOI
http://www.det.mmu.ac.uk/staff/travis/open/subject/64ET1516_E/NOTES/S_JFET____TUT_2p.pdf
http://www-personal.engin.umd.umich.edu/~fmeral/ELECTRONICS II/09%c3-FET Project/JFET_Project.pdf
JFET BIASING TUTORIAL BY W7ZOI
hello.
there are some articles...........e.g.
FET Preamplifier, Part 1
and you can search in the forums here...........musical instruments and so on....
greetings.............
there are some articles...........e.g.
FET Preamplifier, Part 1
and you can search in the forums here...........musical instruments and so on....
greetings.............
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