As you know, in Spice, transistor instances of the same model are exactly the same transistor. This gives perfectly good matching that doesn't exist in the real world.
I need to investigate about the effects of transistors mismatch in a balanced circuit design.
How can I make alternate transistors representative of real ones coming from the same batch.
1) I made one with 5% more Hfe by increasing BF and BR, are they other parameters I should skew ?
2) I don't find a parameter for Vbe, I guess it is hidden in some parameter. How to a make a transistor with a lower Vbe ?
3) I suspect real transistors have their parameters skewed, following a same logic, like:
Hfe +5% and Vbe -5% and Early voltage ( Vfa, Vra ) +? -? 5% and so on. Does this make sens ?
4) If this makes sens, how do I go to make a "+5%" transistor ?
5) If this does not make sens, should I go making many alternate transistors, one for each parameter ?
LTSpice and Tina users, thanks for your attention.
I need to investigate about the effects of transistors mismatch in a balanced circuit design.
How can I make alternate transistors representative of real ones coming from the same batch.
1) I made one with 5% more Hfe by increasing BF and BR, are they other parameters I should skew ?
2) I don't find a parameter for Vbe, I guess it is hidden in some parameter. How to a make a transistor with a lower Vbe ?
3) I suspect real transistors have their parameters skewed, following a same logic, like:
Hfe +5% and Vbe -5% and Early voltage ( Vfa, Vra ) +? -? 5% and so on. Does this make sens ?
4) If this makes sens, how do I go to make a "+5%" transistor ?
5) If this does not make sens, should I go making many alternate transistors, one for each parameter ?
LTSpice and Tina users, thanks for your attention.
Bless you for recognizing SPICE's stupidity.
Old-school analog engineers said you should know how to estimate things to a fine point before you turn to SPICE to make 8-digit reports to impress your boss. You can do all this on thumbs and slide-rule.
I'm a cave-man. I suspect others know the features in fancy-SPICE to force diversity in model parameters. There is a .MC card, Monte Carlo, which randomly varies parameters within limits I have never known how to input.
As basic sanity-check, replace your transistors with *different* transistors. If the circuit is holistic, it will work nearly the same, NO big difference between 2N2222 and 2N3904. Oh, a 20mV difference in Vbe, though any "good" circuit should tolerate that unless fine DC accuracy matters. OTOH I see around here 8-digit SPICE reports that clearly will NOT work if the parts are not EXACTLY like the model.
Another dummy test is to put a 10mV battery in series with key Bases, faking a 10mV difference in Vbe. Holistic circuits will hardly notice. Maybe a 2% difference in reported currents, which should not matter.
You should *know* basic transistor theory. Vbe comes directly from Is, Thermal Saturation Current. When you force less Vbe, you get less current. What if Vbe is taken to zero? You do not get zero current! You get a really small current (due to thermal agitation) which we can't measure, but we can extrapolate from Vbe versus Ie.
Is is really "junction area". Doping, leakage and other things affect it, but you can think of "area". Printers can control ink to a few percent, and chipmakers can too. A given part/process is likely to have +/-5% control of area. This works out (I think) to 5mV variation of Vbe. Clearly many stable processes do better than this in a bucket of parts. Dies made in different times and places will differ more.
The (SPICE!) report below shows this. Two transistors, one bigger than the other. In fact when you get Vbe down to ZERO the current goes way off. But note the very long flat slant. If you hold your ace of spades to the screen, this slant extrapolates to essentially the Is values *in the SPICE model* used. And the bigger part at the same Vbe makes more current; or at the same current, a lower Vbe.
Old-school analog engineers said you should know how to estimate things to a fine point before you turn to SPICE to make 8-digit reports to impress your boss. You can do all this on thumbs and slide-rule.
I'm a cave-man. I suspect others know the features in fancy-SPICE to force diversity in model parameters. There is a .MC card, Monte Carlo, which randomly varies parameters within limits I have never known how to input.
As basic sanity-check, replace your transistors with *different* transistors. If the circuit is holistic, it will work nearly the same, NO big difference between 2N2222 and 2N3904. Oh, a 20mV difference in Vbe, though any "good" circuit should tolerate that unless fine DC accuracy matters. OTOH I see around here 8-digit SPICE reports that clearly will NOT work if the parts are not EXACTLY like the model.
Another dummy test is to put a 10mV battery in series with key Bases, faking a 10mV difference in Vbe. Holistic circuits will hardly notice. Maybe a 2% difference in reported currents, which should not matter.
You should *know* basic transistor theory. Vbe comes directly from Is, Thermal Saturation Current. When you force less Vbe, you get less current. What if Vbe is taken to zero? You do not get zero current! You get a really small current (due to thermal agitation) which we can't measure, but we can extrapolate from Vbe versus Ie.
Is is really "junction area". Doping, leakage and other things affect it, but you can think of "area". Printers can control ink to a few percent, and chipmakers can too. A given part/process is likely to have +/-5% control of area. This works out (I think) to 5mV variation of Vbe. Clearly many stable processes do better than this in a bucket of parts. Dies made in different times and places will differ more.
The (SPICE!) report below shows this. Two transistors, one bigger than the other. In fact when you get Vbe down to ZERO the current goes way off. But note the very long flat slant. If you hold your ace of spades to the screen, this slant extrapolates to essentially the Is values *in the SPICE model* used. And the bigger part at the same Vbe makes more current; or at the same current, a lower Vbe.
Attachments
I haven’t tried this myself, but it seems quite doable by creating two models of the same part, say 2n2222_1 and 2n2222_2 and use the .step command to step through the parameters of interest. Below is taken from the LTSpice Help file:
Code:
.STEP -- Parameter Sweeps
This command causes an analysis to be repeatedly performed while stepping the temperature, a model parameter, a global parameter, or an independent source. Steps may be linear, logarithmic, or specified as a list of values. <snip>
Example: .step NPN 2N2222(VAF) 50 100 25
Step NPN model parameter VAF from 50 to 100 in steps of 25.
Example: .step temp -55 125 10
Step the temperature from -55°C to 125°C in 10-degree step. Step sweeps may be nested up to three levels deep.
Thanks, now I see clearly how to deal with Vbe.
For a +5% BF BR transistor what x% IS would make sense? What y% for Early effect VFA VRA ?
I do not know how the various parameters relate in a Bjt. Some laws of solid state physics, make those dependent in some ways, I presume.
For a +5% BF BR transistor what x% IS would make sense? What y% for Early effect VFA VRA ?
I do not know how the various parameters relate in a Bjt. Some laws of solid state physics, make those dependent in some ways, I presume.
One super easy way to vary the slope of Ice vs Vce (which is called "ro" in the hybrid pi model used for hand analysis), and discussed as "The Early Effect" is some books (named after James Early of Fairchild), is to connect a resistor from collector to emitter in the simulation. This resistor is in parallel with whatever "ro" is programmed into the SPICE model of the transistor. Presto, you now have external control of the effective ro. You can .STEP it however you like. Naturally you must connect a huge phony-baloney capacitor in series with this phony-baloney resistor, to prevent it from changing the dc bias point. For audio circuits, choose C > [(500 seconds) / R] and you'll be very safe.
This little stunt turns out to be especially useful with a very large proportion of LTSPICE MOSFETs, whose as-supplied-by-Linear-Technology spice models happen to set ro = infinity (!). Most of those MOSFET models were extracted and built for use as high current switches, where vds is much MUCH smaller than vgs.
This little stunt turns out to be especially useful with a very large proportion of LTSPICE MOSFETs, whose as-supplied-by-Linear-Technology spice models happen to set ro = infinity (!). Most of those MOSFET models were extracted and built for use as high current switches, where vds is much MUCH smaller than vgs.
Junction area.
It might very well be what I am looking for to relate parameters of Bjts from a same batch.
Is, hence Vbe relates to junction area. Do you know how other parameters relate to junction area ( Beta, Early voltage, ? ). I see about parameters where simple geometry comes in like, re rb and capacitors, when carrier density and quantum mechanics comes in that is another story.
Spice is no more than a calculator, how it fits with realities is entirely up to the user.
BTW. Integrated circuit designers, sure know very well how to deal with transistor instances in simulation.
With identical transistors there is no way to optimize common mode and power supply ripple rejection.
With identical transistor, simulation doesn' t give any usable result. That is the issue I am stuck.
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The transistor area can be specified after the transistor part number. So in LTspice you can change
2N2222
to
2N2222 area=1.05
which models a 5% increase in transistor area. This also works with the temp parameter to change static junction temperature. To include this parameter in monte carlo analysis you can use
2N2222 area={mc(1,0.05)}
Where 1 is default area and 0.05 is the tolerance for the variation. To activate the Monte Carlo simulation you need to step the "run" parameter using for instance:
.step param run 1 100 1
Which will generate 100 steps with random deviations of area within tolerance.
Area doesn't affect Bf or Vaf. For that you need to add monte carlo statements to the SPICE model for each parameter you want to change.
2N2222
to
2N2222 area=1.05
which models a 5% increase in transistor area. This also works with the temp parameter to change static junction temperature. To include this parameter in monte carlo analysis you can use
2N2222 area={mc(1,0.05)}
Where 1 is default area and 0.05 is the tolerance for the variation. To activate the Monte Carlo simulation you need to step the "run" parameter using for instance:
.step param run 1 100 1
Which will generate 100 steps with random deviations of area within tolerance.
Area doesn't affect Bf or Vaf. For that you need to add monte carlo statements to the SPICE model for each parameter you want to change.
I do not need Monte Carlo in the simulation I want to do presently. I want to keep control of the transistor mismatch, I do not want it, to be random. My objective is to calculate the effect of mismatch over power supply rejection.
Thanks, I was not aware of the "area" parameter in Spice, an interesting feature, I will look into its effect on the transistor characteristics. I'll use your .asc file, stepping "area".
I just got an idea for a workaround. What about programming junction temperature to represent different transistors. Temp is not made for that, but varies Hfe and Vbe ( and more ), who knows, may be Temp will give me different transistors as if coming from the same batch ? And it gives a way to control the amount of mismatch. What do you think ?
Thanks, I was not aware of the "area" parameter in Spice, an interesting feature, I will look into its effect on the transistor characteristics. I'll use your .asc file, stepping "area".
I just got an idea for a workaround. What about programming junction temperature to represent different transistors. Temp is not made for that, but varies Hfe and Vbe ( and more ), who knows, may be Temp will give me different transistors as if coming from the same batch ? And it gives a way to control the amount of mismatch. What do you think ?
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There exists a way to step through a list of transistor part numbers. Simulation1 sets all transistors marked with "FLAG" to be 2N2222A. Simulation2 sets all FLAG transistors to BD139. Simulation3 sets them all to 2SC945. Simulation4 sets them all to ZTX696B. etc. It's pretty deeply buried inside the "Ltspice Wiki", in the section called Workarounds or Cute Tricks or some kind of similar title.
That is actually what I was going to suggest, but I went for a more robust method. You can use
2N2222 temp=30
Or so to change the static junction temperature. This will vary Beta according to the exponent Xtb, Vbe and other stuff, but IIRC it doesn't affect Early voltage.
Area=2 is exactly like having 2 transistors in parallel. Vaf is a relative parameter, so it doesn't change when you put transistors in parallel. You can also use the parameter
2N2222 M=2
To represent 2 transistors in parallel. I don't know exactly how this differs from the area parameter if at all. For diodes and other 2-terminal components you can use N=2 to represent 2 in series.
Thanks for your insigts in Bjts variations and hints to implement these in Spice simulation. I realize my idea of using Temp is not so good. I think it is not consistant with known values of the Tempco for Hfe and Vbe. From manufacturing there are very large Hfe variations that would ask for very large Temp variations, then Vbe variations will likel be unrealistic. However it might be all right for hand matched transistors, where I expect to screen them for pairs: 1mV Vbe matched and 5% Hfe matched. I have not checked yet on this point with LTSpice.
You should probably browse through the "examples" folder provided in LTspice.
The wiki is also a good source, and of course the Yahoo LTspice group is "the" reference, but it is rather messy and inconvenient.
Note that the physical junction area is not going to vary much for a given process of a specific manufacturer.
However, the characteritics like Hfe, Vaf, etc are nevertheless going to change enormously depending on doping, mask alignment, etc.
Very much more than 5%... even for sorted transistors like BC547, A, B, C
The wiki is also a good source, and of course the Yahoo LTspice group is "the" reference, but it is rather messy and inconvenient.
Note that the physical junction area is not going to vary much for a given process of a specific manufacturer.
However, the characteritics like Hfe, Vaf, etc are nevertheless going to change enormously depending on doping, mask alignment, etc.
Very much more than 5%... even for sorted transistors like BC547, A, B, C
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