I saw an interesting article on clock buffers - specifically the impact of opamps on clock skew and jitter versus using series of NOT/inverter gates. The article demonstrated that the NOT gates (perhaps due to being an opamp Schmitt trigger configuration?) having less slew and less jitter. The result is that a series of NOT gates performed better than an opamp as a buffer.
I'll try to find the article - IIRC it was a Texas Instruments article. However has anyone tried/used this?
I'll try to find the article - IIRC it was a Texas Instruments article. However has anyone tried/used this?
I recall Andrea Mori showing phase noise measurements with a clock buffer and with an inverter and the inverter returned much better numbers in the area of interest which was at lower freqs. I doubt the clock buffer was an opamp though, I rather think it was a comparator like LT1016. So I should call it a 'clock slicer' rather than a clock buffer.
I may be common practice in vlsi but being the padwan it was eye opening the impact it has. Maintaining pulse width and accuracy (possibly trading amplitude error that can be recovered by quadrature).
Not gates are faster and have less jitter than any other logic gates. They should not be Schmitt triggered. A commonly used low cost part is 74LVC1G04. Generally speaking smaller packages offer less inductance and are faster. Higher power and faster logic families tend to be faster and lower jitter as well.
Its also possible to use unbuffered versions if load capacitance is low. Unbuffered devices have a U in the part number (e.g. 74LVC1GU04). https://www.ti.com/lit/an/scha004/scha004.pdf
Some info on logic families at: https://www.ti.com/lit/ug/scla013d/scla013d.pdf?ts=1663240921283&ref_url=https%3A%2F%2Fwww.google.com%2F
One of the very best clock buffers is PL133-27. An also very good non-inverting 4-output clock buffer is NB3L553, which Andrea uses in FIFO_Lite.
http://ww1.microchip.com/downloads/en/DeviceDoc/PL133-27.pdf
https://www.onsemi.com/pdf/datasheet/nb3l553-d.pdf
You may find that using linear bypass caps with high performance clock buffers can have some audible benefits, perhaps mostly so for DSD (which is more said to be jitter sensitive than PCM). This of course assumes clocking is ultra low phase noise before getting to the buffer input.
Its also possible to use unbuffered versions if load capacitance is low. Unbuffered devices have a U in the part number (e.g. 74LVC1GU04). https://www.ti.com/lit/an/scha004/scha004.pdf
Some info on logic families at: https://www.ti.com/lit/ug/scla013d/scla013d.pdf?ts=1663240921283&ref_url=https%3A%2F%2Fwww.google.com%2F
One of the very best clock buffers is PL133-27. An also very good non-inverting 4-output clock buffer is NB3L553, which Andrea uses in FIFO_Lite.
http://ww1.microchip.com/downloads/en/DeviceDoc/PL133-27.pdf
https://www.onsemi.com/pdf/datasheet/nb3l553-d.pdf
You may find that using linear bypass caps with high performance clock buffers can have some audible benefits, perhaps mostly so for DSD (which is more said to be jitter sensitive than PCM). This of course assumes clocking is ultra low phase noise before getting to the buffer input.
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For what it's worth LMK1C10x has even lower jitter than PL133 or NB3L553. Available in 2 to 4 outputs.
Yep, I noted that isolators increase issues too - a logic gate through the isolating capacitance and then a Schmitt trigger on the other side (the basic principle) to provide the full toggle.
I'll look into those. I can then span multiple outputs using the logic gates.
I suspect I'll have to simply try a small matrix board prototype looking at Andrea's thread and use a voltage reference and BJT for power regulation on the same board.
I'll look into those. I can then span multiple outputs using the logic gates.
I suspect I'll have to simply try a small matrix board prototype looking at Andrea's thread and use a voltage reference and BJT for power regulation on the same board.
LMK1C10x may have lower jitter from 12kHz offset and above, but not necessarily known for lower close-in phase noise?
According to the datasheet it has much lower additive jitter than PL133 or NB3L553 in the same integration range.
Okay, but its 1/f noise that can limit close-in performance. Don't know if anyone has measured those parts down to .1Hz offset?
https://www.ieee.li/pdf/essay/phase_noise_basics.pdf
Some people feel that its additive phase noise in the band from 1Hz to 10Hz offset from the carrier that humans are most sensitive to. Not aware of a published study on it though.
https://www.ieee.li/pdf/essay/phase_noise_basics.pdf
Some people feel that its additive phase noise in the band from 1Hz to 10Hz offset from the carrier that humans are most sensitive to. Not aware of a published study on it though.
You referring to taking an FFT and guesstimating skirt width? You did show that Vref noise and clock phase noise both impact steady state skirt width.
That shows the close-in phase noise at DAC output. I have not made any guesses or calculations regarding absolute values as that is irrelevant. You can try the same measurement with your own DAC and whatever clocks you are using. Much more useful than looking at Timepod measurements of separate clocks. Timepod does not measure DAC output which is what you hear.
Using LVCMOS logic to buffer clocks (BCK, LRCK, MCK etc.) is commonplace in the industry, especially when many devices (e.g. DACs) are fed with the same signal. But opamps would be a poor approach, as speed / propagation delay is more important than linearity / accuracy, in this application.
One may use any of the regular CMOS families like HC, HCT, HCU, LV etc. They all have enough speed (tp<10ns) for most applications. 74xx04 is the simplest, fastest and cheapest of them all. Just do not leave any unused inputs floating, instead connect them to a valid voltage like Vcc, GND, or the neighbouring (logic) input.
One may use any of the regular CMOS families like HC, HCT, HCU, LV etc. They all have enough speed (tp<10ns) for most applications. 74xx04 is the simplest, fastest and cheapest of them all. Just do not leave any unused inputs floating, instead connect them to a valid voltage like Vcc, GND, or the neighbouring (logic) input.
Maybe some of the readers would be interested to know how spectral skirt widening in a steady-state FFT is caused both by clock close-in phase noise and by Vref noise? Perhaps interesting to note that the time-domain mechanisms are quite different.
Both clock close-in phase noise and Vref noise impact the noise skirts. This makes it a useful measurement of the overall quality of the implementation (Vref, clock & clock buffer phase noise). Much better than the steady-state Timepod measurement of the clock separately.
Timepod is quantitative. FFT skirts are evaluated subjectively, although not claiming subjective measurements as problematic.
Regarding how FFT skirts are affected by close-in phase noise, its because of timing errors. FFT skirts are affected by Vref noise due to amplitude errors. For small errors, one type of error can be deemed approximately equivalent to the other. Doesn't mean they necessarily sound the same to a human, especially during statistically expected moments where errors happen to be larger. The time-domain nature of such errors cannot be exactly represented by a phase-free, time-averaged, windowed FFT.
Regarding how FFT skirts are affected by close-in phase noise, its because of timing errors. FFT skirts are affected by Vref noise due to amplitude errors. For small errors, one type of error can be deemed approximately equivalent to the other. Doesn't mean they necessarily sound the same to a human, especially during statistically expected moments where errors happen to be larger. The time-domain nature of such errors cannot be exactly represented by a phase-free, time-averaged, windowed FFT.
With Timepod you can measure the clock as stand-alone. It tells nothing about the final output from DAC.
The measurement I showed can be performed without windowed FFT. Actually it was originally measured with 32M FFT without windowing which of course is even more telling. Unfortunately I do not have that software myself so I cannot show those measurements. REW does not have such capability.