Now that it is increasingly difficult to obtain high-quality small-signal semiconductors as well as P-type semiconductors, could the following DIY-at-home approach be a potential alternative?
Homemade Silicon ICs / Computer Chips - YouTube
First IC 🙂 – Sam Zeloof
Upgraded Homemade Silicon IC Fab Process - YouTube
Second IC 🙂 – Sam Zeloof
kind regards, jonathan
Homemade Silicon ICs / Computer Chips - YouTube
First IC 🙂 – Sam Zeloof
Upgraded Homemade Silicon IC Fab Process - YouTube
Second IC 🙂 – Sam Zeloof
kind regards, jonathan
The guy is either full of ****, or the videos are fake, probably filmed in an university lab, and now he's having lots of fun recording feedback.
- Photoresist in white light
- No idea how he alignes the masking layers, he shows only what appears to be UV exposure (BTW, what UV source is he using???)
- No oxidation step before litography.
- Etching in nitric acid, what??? that's for cleaning and photoresist removal.
- Where are the etching step for polysilicon?
- 1% HF as stated won't etch a iota of thermally grown SiO2, you need a concentrated HF buffered solution, I wouldn't keep that in the house, see "Breaking Bad".
- No polysilicon deposition, this is a huge issue. Buying MOS grade wafers with 10nm of oxide and 300nm of polysilicon, these costs 1000's of dollars a pop, if you can get them in singles, only to break them in chip sizes.
- No gate oxide process and no control of the Si/SiO2 interface, that's critical for MOS devices.
- Pouring water from a bottle, that's as stupid as it gets.
- NMOS poly gate process, it is impossible to control the contamination without serious cleanings before/after each process step.
Even when using second had 20 years old equipment, I can't imagine the full setup would cost less than a few hundred thousands dollars. Not to mention consumables like DI water, N2, Oxygen, gaseous hydrochloric acid, Silane (God forbid at home, this gas explodes like a nuke in contact with air) for polysilicon deposition, etc... etc... etc... An expensive hobby indeed
P.S. The process flow on his blog is BS as well... Like how to get from "Dope source/drain" to "Etch poly gate", the polysilicon and oxide selectively just magically selectively vanishes where he no longer wants it. Count the masks, I get about 6 instead the claimed 4. The sad thing is that people that can believe such stories do exist, and some are even introducing themselves as "microelectronics engineers".
P.P.S. The guy which is building his own vacuum tubes, that's indeed instructive and the process makes sense (although I would not expect some outstanding quality).
- Photoresist in white light
- No idea how he alignes the masking layers, he shows only what appears to be UV exposure (BTW, what UV source is he using???)
- No oxidation step before litography.
- Etching in nitric acid, what??? that's for cleaning and photoresist removal.
- Where are the etching step for polysilicon?
- 1% HF as stated won't etch a iota of thermally grown SiO2, you need a concentrated HF buffered solution, I wouldn't keep that in the house, see "Breaking Bad".
- No polysilicon deposition, this is a huge issue. Buying MOS grade wafers with 10nm of oxide and 300nm of polysilicon, these costs 1000's of dollars a pop, if you can get them in singles, only to break them in chip sizes.
- No gate oxide process and no control of the Si/SiO2 interface, that's critical for MOS devices.
- Pouring water from a bottle, that's as stupid as it gets.
- NMOS poly gate process, it is impossible to control the contamination without serious cleanings before/after each process step.
Even when using second had 20 years old equipment, I can't imagine the full setup would cost less than a few hundred thousands dollars. Not to mention consumables like DI water, N2, Oxygen, gaseous hydrochloric acid, Silane (God forbid at home, this gas explodes like a nuke in contact with air) for polysilicon deposition, etc... etc... etc... An expensive hobby indeed
P.S. The process flow on his blog is BS as well... Like how to get from "Dope source/drain" to "Etch poly gate", the polysilicon and oxide selectively just magically selectively vanishes where he no longer wants it. Count the masks, I get about 6 instead the claimed 4. The sad thing is that people that can believe such stories do exist, and some are even introducing themselves as "microelectronics engineers".
P.P.S. The guy which is building his own vacuum tubes, that's indeed instructive and the process makes sense (although I would not expect some outstanding quality).
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Doubtful that all the toxic chemicals necessary could be legally bought, or disposed of after use,
at least in the USA. We took a full semester back in undergrad fab class to make a few functioning
diodes and transistors, all of which were easily visible to the eye.
at least in the USA. We took a full semester back in undergrad fab class to make a few functioning
diodes and transistors, all of which were easily visible to the eye.
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You need hobby quantities, not industrial ones. locate and store a reasonable quantity.
Silicon fabrication is difficult.
Or contact some companies actually running silicon foundries, their minimum quantities might just make you think of changing your design to one where easily available parts are used.
Silicon fabrication is difficult.
Or contact some companies actually running silicon foundries, their minimum quantities might just make you think of changing your design to one where easily available parts are used.
Perhaps 10 years ago I and a few other manufacturer friends were in touch with a Japanese company who had the technology necessary to make a 2SJ74-class P-JFET (and matching N-JFET). I don't recall the precise numbers, but I think the minimum cost was around $USD 200,000.
Split three ways the financial damage would have been $6x000. Doable, but ultimately we didn't carry through.
kind regards, jonathan
Split three ways the financial damage would have been $6x000. Doable, but ultimately we didn't carry through.
kind regards, jonathan
And that was for process development only, the fab equipment and consumables were 99.9% already in place. Go figure .
.Sam here, I made those chips, youtube vids, etc. I normally would not respond to something like this but it's a good opportunity to see what I've failed to explain well and respond to misconceptions.
-Many photoresists can be exposed to white light for a matter of minutes to hours. Typically they have exposure doses around 200mJ/cm^2 of <390nm light. My LED room lighting has <1mW at those wavelengths. Depends on the PR and sensitivity though, I checked mine with a spectrometer and UV power meter. See my previous vids done in the dark before I knew this. Modern chemically amplified photoresists may be more sensitive so this is not possible, idk. There's incentive to make the resist as sensitive as possible so your exposure times are low and throughput is high.
-Alignment is shown in my video titled "Maskless Photolithography Stepper for Homemade Chips". A UV filter is used to project the image in red onto the chip (also shown in the linked video). When it's time to start exposure, I remove the filter and the image is projected in blue (UV). The mercury vapor arc lamp of a stock DLP projector has plenty of UV if you remove filters inside.
-This comment about "no oxidation step before lithography" does not make sense.
-Nitric acid (or SF6 RIE) is used to etch the polysilicon. HNO3+HF was the original formulation used by Federico Faggin in the 70s when he invented the self-aligned polysilicon gate process.
-Room temp 1.5% HF etches 500nm of thermally grown oxide in about 25 minutes, see my previous videos demonstrating this step and also Jeri Ellsworth's vids.
-I bought 25 of these wafers on ebay for $45. Yes, it is not sustainable, but I mentioned a method of depositing amorphous silicon and laser annealing, this has been done in a lot of papers. A DIYer could strap a 405nm laser diode to a 3d printer as XY stage and do that.
-I grew the gate oxide for my first chip, described here First IC 🙂 – Sam Zeloof
-It's DI water from a wash bottle, this is proper
-I hate to see "impossible" statements like this. Usually they are uninformed uncreative and short sighted. I mention my modified process flow, which has some drawbacks, but never exposes the silicon in the channel region (its always protected by oxide and poly.)
Bad chemicals like the gaseous hydrochloric acid and silane you mention are not required. By changing the ground rules and relaxing requirements (I don't care about fab throughput or yield), new things become possible and I can do alternative processes that the industry would not consider because they are too slow or not scalable.
P.S. There are really only 4 masks. The step you describe as problematic is the Gate mask shown above in the blog post. First mask defines the doped regions, second defines the gate, third defines the contact, last defines the metal. Not 6.
Hopefully this helps clear things up!
-Many photoresists can be exposed to white light for a matter of minutes to hours. Typically they have exposure doses around 200mJ/cm^2 of <390nm light. My LED room lighting has <1mW at those wavelengths. Depends on the PR and sensitivity though, I checked mine with a spectrometer and UV power meter. See my previous vids done in the dark before I knew this. Modern chemically amplified photoresists may be more sensitive so this is not possible, idk. There's incentive to make the resist as sensitive as possible so your exposure times are low and throughput is high.
-Alignment is shown in my video titled "Maskless Photolithography Stepper for Homemade Chips". A UV filter is used to project the image in red onto the chip (also shown in the linked video). When it's time to start exposure, I remove the filter and the image is projected in blue (UV). The mercury vapor arc lamp of a stock DLP projector has plenty of UV if you remove filters inside.
-This comment about "no oxidation step before lithography" does not make sense.
-Nitric acid (or SF6 RIE) is used to etch the polysilicon. HNO3+HF was the original formulation used by Federico Faggin in the 70s when he invented the self-aligned polysilicon gate process.
-Room temp 1.5% HF etches 500nm of thermally grown oxide in about 25 minutes, see my previous videos demonstrating this step and also Jeri Ellsworth's vids.
-I bought 25 of these wafers on ebay for $45. Yes, it is not sustainable, but I mentioned a method of depositing amorphous silicon and laser annealing, this has been done in a lot of papers. A DIYer could strap a 405nm laser diode to a 3d printer as XY stage and do that.
-I grew the gate oxide for my first chip, described here First IC 🙂 – Sam Zeloof
-It's DI water from a wash bottle, this is proper
-I hate to see "impossible" statements like this. Usually they are uninformed uncreative and short sighted. I mention my modified process flow, which has some drawbacks, but never exposes the silicon in the channel region (its always protected by oxide and poly.)
Bad chemicals like the gaseous hydrochloric acid and silane you mention are not required. By changing the ground rules and relaxing requirements (I don't care about fab throughput or yield), new things become possible and I can do alternative processes that the industry would not consider because they are too slow or not scalable.
P.S. There are really only 4 masks. The step you describe as problematic is the Gate mask shown above in the blog post. First mask defines the doped regions, second defines the gate, third defines the contact, last defines the metal. Not 6.
Hopefully this helps clear things up!
Sir, you obviously have some elementary knowledge of semiconductor processing, likely acquired in an undergraduate course, but otherwise I still believe you are a crook looking for a cheap source of youtube and web site hits. I cannot be bothered to further expand on the crap in the videos and the comments above, so please save your BS for those who enjoy such nonsense. "Depositing amorphous silicon and laser annealing", hear, hear, just like that, in your garage, no silane and an excimer laser source purchased from EBay for $10
. Some lies are so big they are almost impossible to address...
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And just to avoid another parade, here's something you won't find in Wikipedia: amorphous polysilicon laser crystallization requires temperatures in excess of 700 degrees centigrades, while scanning the surface with a laser beam of more than 200 J/cm^2 The process obeys the Arrhenius activation energy law, anything less than a combination as above will not crystallize.
I suppose you could heat the chips on an electric heater while manually walking a high power laser beam on the surface for a few hours, with much care to avoid melting the chip.
I suppose you could heat the chips on an electric heater while manually walking a high power laser beam on the surface for a few hours, with much care to avoid melting the chip
.
Just checked Jeri Ellsworth's video you quoted, so you claim etching MOS devices oxide(s) in Rust Stain Remover from Home Depot and get functional MOS devices, this becomes fascinating .
For your education, 40% HF (which is a very high concentration, impossible to buy for DIY) has an etch rate of approximately 800 nm/min at a temperature of 21 degrees centigrade. Unfortunately unbuffered HF also etched the photoresist, so assuming your stain remover indeed etches 500nm in 25minutes, the resist will be long gone by then, photorezist is not tougher than the rust stains. You can't etch any oxides more than say 50-100 nm with any photoresist selectivity without using BOE 7:1 or 10:1 (NHF4 + 49% HF). FYI, 1% HF is usually needed for a quick dip to remove the (contaminated) native oxide on silicon, just before critical oxidation processes (like the gate oxide).
.For your education, 40% HF (which is a very high concentration, impossible to buy for DIY) has an etch rate of approximately 800 nm/min at a temperature of 21 degrees centigrade. Unfortunately unbuffered HF also etched the photoresist, so assuming your stain remover indeed etches 500nm in 25minutes, the resist will be long gone by then, photorezist is not tougher than the rust stains. You can't etch any oxides more than say 50-100 nm with any photoresist selectivity without using BOE 7:1 or 10:1 (NHF4 + 49% HF). FYI, 1% HF is usually needed for a quick dip to remove the (contaminated) native oxide on silicon, just before critical oxidation processes (like the gate oxide).
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See my blog post from 2018 discussing the buffered oxide etch recipe. Resist adhesion and etching in HF was a big problem when I first started this. SiO2 Patterning – Sam Zeloof
Lots of details like that I can't mention in a 5 min youtube vid but its published so others can replicate.
The thickest oxide on Z2 is the 10nm gate oxide, there is no thick oxide anyway bc I used poly for dopant masking and hardened photoresist for inter layer dielectric. For the recent chips I did most of the etching with my RIE anyway which has great selectivity with my 2um resist layers Etching Silicon with Plasma - Reactive Ion Etching (RIE) - YouTube
Lots of details like that I can't mention in a 5 min youtube vid but its published so others can replicate.
The thickest oxide on Z2 is the 10nm gate oxide, there is no thick oxide anyway bc I used poly for dopant masking and hardened photoresist for inter layer dielectric. For the recent chips I did most of the etching with my RIE anyway which has great selectivity with my 2um resist layers Etching Silicon with Plasma - Reactive Ion Etching (RIE) - YouTube
Stop digging yourself in an ever deeper hole 😀.
So no oxide thicker than the 10nm, no field oxide, but instead photoresist??? And how do you avoid field inversion under this "oxide"??? And how do you bond wires on metal over 10nm of oxide or soft photoresist without shorting everything to the substrate???
You go ahead and have fun fooling people with videos and photos, the one with a fan blowing water vapor from a petri dish in the oxidation tube is amazing, I'm sure that oxide will be MOS grade. I've had enough of this BS, over and out.
So no oxide thicker than the 10nm, no field oxide, but instead photoresist??? And how do you avoid field inversion under this "oxide"??? And how do you bond wires on metal over 10nm of oxide or soft photoresist without shorting everything to the substrate???
You go ahead and have fun fooling people with videos and photos, the one with a fan blowing water vapor from a petri dish in the oxidation tube is amazing, I'm sure that oxide will be MOS grade
. I've had enough of this BS, over and out.
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Thanks A LOT, much respect.
It is refreshing (and unusual) to see people who roll up their sleeves and DO THINGS.
Keep up the good (impressive) work , congratulations.
As a practical comparison: in the late 70´s, Communist Chinese participated in an Industrial/Technology Exposition here in Argentina.
It was way *before* they opened to USA who massively injected Capital and Technology, and they had no hard currency to buy "outside" so they had to rely on homegrown stuff. Literally.
They were very proud showing some oscilloscopes made at some State run factory (of course, what else?) "attached" to some University.
I asked them, not surprised at learning they made their own cathode ray tubes because Chinese had Tube factories since forever BUT was flabbergasted when they told me "the University grew their own transistors, including High Frequency and High Voltage ones, both for own use and to supply attached Factory in quantity".
And they explained a manufacturing process very similar to yours.
A note for those interested: the photolitography and oxide etching steps described in his blog SiO2 Patterning – Sam Zeloof are mostly correct (some minor inconsistencies, photoresist hard bake follows exposure and development, after the photoresist spin there's a "soft bake" step) and described in every microelectronics fab undergraduate course.
For those that somehow can get HDMS (Hexamethyldisilazane) to prime the chips/wafers be aware that HMDS is an extremely flammable liquid and vapor, is toxic in contact with skin, is toxic if inhaled, is harmful if swallowed, causes severe skin burns and eye damage, may cause severe damage to organs through prolonged or repeated exposure. Disposing the used HDMS without processing is a big problem, since extremely small quantities, in the PPM range, are deadly for aquatic life. Pouring this in the sewer is likely (or should be) a crime.
You have been warned.
For those that somehow can get HDMS (Hexamethyldisilazane) to prime the chips/wafers be aware that HMDS is an extremely flammable liquid and vapor, is toxic in contact with skin, is toxic if inhaled, is harmful if swallowed, causes severe skin burns and eye damage, may cause severe damage to organs through prolonged or repeated exposure. Disposing the used HDMS without processing is a big problem, since extremely small quantities, in the PPM range, are deadly for aquatic life. Pouring this in the sewer is likely (or should be) a crime.
You have been warned.
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In post 16 I should have said that I plan to follow the thread. No plans to duplicate the process. Dimethyl death is not in my future. Bill
Same here.
I find the whole process and idea very interesting, no way I am trying it at home.
But happy to see that somebody is actually doing it.
I find the whole process and idea very interesting, no way I am trying it at home.
But happy to see that somebody is actually doing it.
Not even hard to find. In fact first hit on Google:
Hexamethyldisilazane reagent grade, ≥99% | 999-97-3
Not cheap but not unaffordable. (FAR cheaper than printer ink.)