Came across a paper sort of similar in nature to Bruno Putzey's work on ferrite distortion/noise in class D amps. Please see attached.
It appears to be something similar to what I have noticed in much lower power DSD dac circuits where ferrite beads are commonly used with the intention of reducing noise problems, but may in actual practice have some adverse side effects by way of adding some distortion/noise of their own.
It appears to be something similar to what I have noticed in much lower power DSD dac circuits where ferrite beads are commonly used with the intention of reducing noise problems, but may in actual practice have some adverse side effects by way of adding some distortion/noise of their own.
Class D amps have output indictors as a part of its filter and these almost always are based on some sort of core (ferrite?) to increase the inductance in order I suppose to keep the size down.
From the pdf:
"...ferrite bead with a rated current of 50mA, a DC resistor of 1.5 Ω and 0.6 mm × 0.3 mm dimensions."
Who puts a "ferrite bead" with the above described properties in series of the output of a proper amp?
This is what is typically used:
https://eu.mouser.com/ProductDetail/Coilcraft/UA8014-ALD?qs=qSfuJ%2Bfl/d4nyyvNNVbELg==
And in later amps these filter components are inside the control loop so taken out of the equation.
I think the document dont provide any insight to todays class d amplifier designers. It seems dated and some of the procedures and setups seems like bad science. It has "class-D" in its title but when the beads are investigated, they use a class A/B amp... crazy,... ;-)
Old "science".... not interesting and basic for any reasonably informed technically inclined in the field.
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From the pdf:
"...ferrite bead with a rated current of 50mA, a DC resistor of 1.5 Ω and 0.6 mm × 0.3 mm dimensions."
Who puts a "ferrite bead" with the above described properties in series of the output of a proper amp?
This is what is typically used:
https://eu.mouser.com/ProductDetail/Coilcraft/UA8014-ALD?qs=qSfuJ%2Bfl/d4nyyvNNVbELg==
And in later amps these filter components are inside the control loop so taken out of the equation.
I think the document dont provide any insight to todays class d amplifier designers. It seems dated and some of the procedures and setups seems like bad science. It has "class-D" in its title but when the beads are investigated, they use a class A/B amp... crazy,... ;-)
Old "science".... not interesting and basic for any reasonably informed technically inclined in the field.
//
If you read the introduction, you know it is about battery-supplied embedded applications. That is, very low power class D amplifiers meant to work without output filter that get a ferrite bead anyway to pass EMC regulations. Still, 1.5 ohm is a lot when the load is 8 ohm.
For THD measurements (section IV) they used a different bead (rated current 2 A, a DC resistor of 50mOhm).
recently ferrite bead manufacturers started to specify the filtering characteristics as a function of dc current. most do not filter anymore at 20% of their rated dc current. That is why many manufacturers prefer to ignore that effect.
Chinese engineers do not bother themselves with nonsense; they either install air inductance or do not install it at all. And they didn’t give a damn about EMR.
What I don't understand here is that there appears to be some basic similarity between a class D amp and a DSD dac. Both use a switch followed by some filtering to reconstruct an analog waveform.
If DSD dacs have considerations with not being able use proper nonsubtractive dither, and if DSD dacs can have fold down artifacts that look like distortion or look like noise on an FFT, then why should class D amps be free of such artifacts?
If class D amps are not free of such artifacts, then are the artifacts typically measured and corrected in some way?
If DSD dacs have considerations with not being able use proper nonsubtractive dither, and if DSD dacs can have fold down artifacts that look like distortion or look like noise on an FFT, then why should class D amps be free of such artifacts?
If class D amps are not free of such artifacts, then are the artifacts typically measured and corrected in some way?
I'm no expert on this, but as far as I know, many class D amplifiers are analogue or at least continuous time. They also use pulse width modulation rather than some variant of pulse density modulation (single-bit sigma-delta modulation (such as DSD) is a kind of time-quantized pulse density modulation). I think you don't get an FM-spectrum with an alias like that.
The few that are digital usually either have poor performance or strong feedback using a low-latency ADC in their feedback path.
The few that are digital usually either have poor performance or strong feedback using a low-latency ADC in their feedback path.
Guess that makes sense in some cases. Some papers in the dropbox llnk at: https://www.dropbox.com/scl/fo/mb53...C3bfbYhQ?rlkey=15v1k5o04r9j0bkd92ifhrfpp&dl=0
seem to suggest the Carrier model is still being used with mostly analog (or highly oversampled) systems only using modulation to produce one-sided PWM. However it appears the greatest concern is with stability, not artifacts.
One of the papers states:
In recent years the application of Field Programmable Gate Array (FPGA) technology to power electronic systems has become popular. These devices open the possibility of emulating analog control loops in the digital domain by oversampling the output signal at a rate significantly higher than the switching frequency. In this type of implementation the control loop as well as the digital pulse-width modulator run at the sampling frequency and the pulse-width modulator is updated at every sampling instant. These current regulators closely emulate analog control loops and offer the advantage of eliminating the transport delays inherent in the regularly-sampled control and modulation processes to a large extent.
During the design of analog (or highly oversampled digital) control loops the model of the pulse-width modulator is traditionally just a simple gain block. This model suggests that infinite control bandwidth can be obtained under certain conditions. However, experience has shown that the design of high-bandwidth control loops based on this linear model are uncertain. Some loops are unstable in simulation and in practice, while the standard linear model predicts that they are perfectly stable. Slightly different loops, designed by the same basic methods, are perfectly stable without any apparent explanation. This paper takes a deeper look at the underlying mechanisms that determine the behaviour of the naturally sampled PWM control loop. It is shown that the interaction between the control loop and the pulse-width modulator is much more involved than the simple linear model would suggest.
...
This paper showed that the interaction between the naturally sampled (or highly oversampled) pulse-width modulator and the control loop is much more complicated than is commonly believed. Even naturally sampled PWM imposes a fundamental bandwidth limitation on the control loop. The sampling behaviour of the modulator was accurately modelled through the application of z-domain techniques. It was found that ripple feedback results in significant variations in the smallsignal gain of the modulator. A novel technique to mitigate the effects of ripple feedback, without limiting the bandwidth, was presented. New z-domain design techniques, that would facilitate the design of the best possible controller within the physical limitations of the PWM process, were developed.
So all of the above possibly being the case, might it be fair to say it looks like the search for artifacts may to some extent have to take a back-seat to (hopefully) achieving stability?
seem to suggest the Carrier model is still being used with mostly analog (or highly oversampled) systems only using modulation to produce one-sided PWM. However it appears the greatest concern is with stability, not artifacts.
One of the papers states:
In recent years the application of Field Programmable Gate Array (FPGA) technology to power electronic systems has become popular. These devices open the possibility of emulating analog control loops in the digital domain by oversampling the output signal at a rate significantly higher than the switching frequency. In this type of implementation the control loop as well as the digital pulse-width modulator run at the sampling frequency and the pulse-width modulator is updated at every sampling instant. These current regulators closely emulate analog control loops and offer the advantage of eliminating the transport delays inherent in the regularly-sampled control and modulation processes to a large extent.
During the design of analog (or highly oversampled digital) control loops the model of the pulse-width modulator is traditionally just a simple gain block. This model suggests that infinite control bandwidth can be obtained under certain conditions. However, experience has shown that the design of high-bandwidth control loops based on this linear model are uncertain. Some loops are unstable in simulation and in practice, while the standard linear model predicts that they are perfectly stable. Slightly different loops, designed by the same basic methods, are perfectly stable without any apparent explanation. This paper takes a deeper look at the underlying mechanisms that determine the behaviour of the naturally sampled PWM control loop. It is shown that the interaction between the control loop and the pulse-width modulator is much more involved than the simple linear model would suggest.
...
This paper showed that the interaction between the naturally sampled (or highly oversampled) pulse-width modulator and the control loop is much more complicated than is commonly believed. Even naturally sampled PWM imposes a fundamental bandwidth limitation on the control loop. The sampling behaviour of the modulator was accurately modelled through the application of z-domain techniques. It was found that ripple feedback results in significant variations in the smallsignal gain of the modulator. A novel technique to mitigate the effects of ripple feedback, without limiting the bandwidth, was presented. New z-domain design techniques, that would facilitate the design of the best possible controller within the physical limitations of the PWM process, were developed.
So all of the above possibly being the case, might it be fair to say it looks like the search for artifacts may to some extent have to take a back-seat to (hopefully) achieving stability?
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It is another application of the old Bruno’s discovery, that small signal gain of comparator depends on the slew rate of the input signal.
If you keep ripples approximately independent from the signal, it makes possible to optimize feedback for higher loop gain.
Smaller variations of the comparator gain allow a bit tighter control on loop stability. Unfortunately, the benefit is not very impressive, IMHO. Single side PWM is not much better than regular one with a triangle wave. At least at high loop gains (above 100dB) I haven’t found any measurable difference.
Using FPGA for audio grade SMPS is very promising. I have designed a demo project of high quality PFC stage fitting into very small and cheap GoWin FPGA. For now it is just a combined verilog+spice simulation.
If you keep ripples approximately independent from the signal, it makes possible to optimize feedback for higher loop gain.
Smaller variations of the comparator gain allow a bit tighter control on loop stability. Unfortunately, the benefit is not very impressive, IMHO. Single side PWM is not much better than regular one with a triangle wave. At least at high loop gains (above 100dB) I haven’t found any measurable difference.
Using FPGA for audio grade SMPS is very promising. I have designed a demo project of high quality PFC stage fitting into very small and cheap GoWin FPGA. For now it is just a combined verilog+spice simulation.
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All of that can be measured/calculated, see this for example:
https://www.diyaudio.com/community/threads/non-linearities-of-cored-inductors.354641/post-6208395
As a rule, passing a significant current through an ungapped or worse, a solid cored inductor is asking for trouble.
I think that elsewhere I made the calculation for a specific ferrite bead; I'll try to locate it
https://www.diyaudio.com/community/threads/non-linearities-of-cored-inductors.354641/post-6208395
As a rule, passing a significant current through an ungapped or worse, a solid cored inductor is asking for trouble.
I think that elsewhere I made the calculation for a specific ferrite bead; I'll try to locate it
It is a well-known, well covered subject. These inductors are designed with the peak current in mind. A random ferrite bead placed somewhere in the power signal path is different: it can or cannot withstand the current.
In the meantime, I have found another thread on the subject, but not the one I had in mind:
https://www.diyaudio.com/community/...nductor-on-a-class-ab-amp.287813/post-4635508
In the meantime, I have found another thread on the subject, but not the one I had in mind:
https://www.diyaudio.com/community/...nductor-on-a-class-ab-amp.287813/post-4635508
There is a difference between core saturation, and the hysteresis distortion Bruno talked about.
I tried 0805 220 ohm Murata ferrite beads at the linear output of my DAC to improve RF immunity.
When replaced with thin film resistors 0805 100ohm, 3rd and 5th harmonics were down 10dB.
Never use ferromagnetic cores (gapped or not) in audio, if they are not inside a feedback loop.
When replaced with thin film resistors 0805 100ohm, 3rd and 5th harmonics were down 10dB.
Never use ferromagnetic cores (gapped or not) in audio, if they are not inside a feedback loop.