First time designing single-ended to balanced line driver

Hello !

Trying my hand at a single-ended to balanced line driver/buffer. See preliminary block diagram below. Main characteristics and design goals:
  • Provide the 12dB gain from -10dBV consumer level to "pro" 4dBu
  • Standard XLR output
  • Able to drive long cables ( 25 ft max maybe? )
  • Bipolar complementary push-pull configuration
  • The cascode input stage's high input impedance allows the source to also drive a regular consumer 47K input in parallel to this circuit
  • Input stage LTP CCS-biased (Vbe referenced)
  • Class A output stage (BD139/BD140)
  • +/-15V regulated power supply (not swown)

single-ended-to-balanced-line-driver.jpg


I have no clue on half of what I'm doing 😛 Does this seem a proper topology? Any unrealistic design goals, perhaps regarding the long cables? Do I need to include a feedback circuit?

Thanks for any insights,
Joris
 
It appears the complementary pair of emitter followers at the output, are at risk of clipping. The signal at NPN emitter cannot fall below zero volts, and the signal at PNP emitter cannot rise above zero volts. Maybe you want to reconsider connecting the 47 ohm resistors to ground (?)

Also, since there's no negative feedback, it will be difficult to calculate the voltage gain from output to input. Among other things, it will vary as output stage Beta varies (the Remitter*Beta term in the gain expression) and Beta varies from unit to unit.
 
Thank you for you reply,

the distortion from that will be horrendous
Can you elaborate on the cause of the distortion? My amplifier's input stage uses this configuration. Wouldn't the single transistor phase splitter input impedance be somewhat low?
Alternatively I could use a long tail pair input stage with the added benefit of GNFB loop connection on the inverting input, but would also loose the high input impedance of the cascode...
 
Last edited:
Thank you Mark for you quick reply. I have removed the ground connection between the output's emitter degeneration resistors. I also removed the CCS loading for the input stage as it would have required two separate adjustable CCSes - one for each polarity. Trying to keep things simple...

single-ended-to-balanced-line-driver v2.jpg

output stage Beta varies (the Remitter*Beta term in the gain expression)
Won't the emitter degeneration resistors "swamp" those variations in Re*Hfe?
 
In the schematic attached to post #1, 2nd stage gain is
  • gm_VAS * Beta_OPS * ((1/gm_OPS) + 47 ohms)
thus gain is directly proportional to Beta_OPS; and Beta is quite variable. (when I wrote Remitter*Beta I was thinking (47R + epsilon)*Beta)
 
Of course the end result is fun. But as a beginner in electronics I like the journey as much and maybe more - learning the basic "blocks" topologies. Spice simulation is a great tool for people like me who learn by bumping into walls 😆

Looking at the IC solution it seems I could have a PCB sent to the fab house by next week and a working preamp by christmas. I would have learned things for sure but the inner workings of the circuit would still be a bit blurred. So I'll still try and simulate discrete stuff and if I at some point break out in tears I'll reach for that IC...
 
Quick look at the circuit shows its a push-pull class B output, so not differential output at all. And one of the output caps is the wrong polarity anyway.
The input stage is not biased into conduction so will distort heavily as its basically class-C.

This task is a job for a dual opamp, one to amplify, one to complement. With discrete devices the output stage can be a single transistor with equal value collector and emitter resistors to give anti-phase outputs, but getting good linearity is much harder.
 
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Does that make more sense? (schematic attached as pdf if needed)

Capture d’écran 2024-09-22 160219.png


What I think is going on so far...
  • Added single transistor phase splitter as suggested in post #3. If a higher input impedance is required a JFet could be used?
  • The bias of the cascode VAS can be set through adjustment of the phase splitter's collector and emitter resistances (here split in two resistors but would be implemented with a trimpot)
  • Biased the second gain stage into class A (T71 and T1 bases sitting at about 1/2 V+ and 1/2 V-, respectively)
  • NFB loop from output stage emitter followers' midpoint to cascode VAS emitters balances the output phases
  • Gain is still a bit shy of the required 12dB (10.5dB)
 

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