Q1 and Q2 needs gate protection at clipping. I would try cascoding them to get a better a better distortion figure.
I would also trim in R5 and R4. It would be better to have equal current in the input transistors, would'nt it?
I would also trim in R5 and R4. It would be better to have equal current in the input transistors, would'nt it?
👍
R4, R5, R6, R7 should stay the same value. They work as AC current mirrors with DC current offset under Q1, Q2. Thus, the current from Q5, Q7 got recycled instead of wasted.
I thought about DC offset, but I prefer to keep AC symmetrical over DC offset. A trim pot would break the AC symmetry.
Did you try varying some of the MOSFET model parameters to get a more realistic view of the distortion figures and sensitivities? If they are all perfectly matched, then that's cheating lol 🙂
I think, they are different ground: chassis- and signal-ground. The R9 is functioning as loop-breaker.
Note the use of different ground symbols on the schematic.
This design by jxdking keeps the low-current small-signal ground separated from the high-current power ground, and returns the signal ground to the power ground via the 10Ω impedance of R9.
The output Zobel filter connects to the power ground rather than small signal ground.
The feedback-loop compensation is very tricky: the C3-C12 and R14-R12 define about 26 dB (20x) closed loop gain too (with enhanced stability at high freq.), but C3-C12 divider seems a little bit a Miller comp., and a little bit a pure single pole compensation with relatve small total cap., and it is closed loop at high frequency without R14-R12 too. A little of each, a little of neither. Good idea!
Jcarr, your interpretation is correct, I've neglected the output ground symbols, because I saw the smaller picture, without clicking.😳
I might have overthought the compensation. C12 might not be necessary. The small loop fed back by C3 has only 2 active devices (in folded cascode) at high frequency. Usually they are stable without C12.
However, there is another concern. When EF3 is driven by high impedance source, it exhibits high frequency ringing. A RC shunt network on the VAS is necessary, if C12 is removed. Please see my next version below.
This is the version I would like to build. I have already ordered the PCB.
I prefer MOSFET output stage over EF3, to keep the PCB minimum, even it might have slight higher THD.
I don't have the evidence that Lateral MOSFET has lower THD than the vertical one. As IRFP ones are widely available, I would like to just stick with them.
2N5551/2N5104 and ZVN0124/ZVP4424 have the same pinout, and they are actually interchangeable throughout in my circuit. Q1, and Q2 can be changed to MOSFET, too.
That would be a full MOSFET amp.
I prefer MOSFET output stage over EF3, to keep the PCB minimum, even it might have slight higher THD.
I don't have the evidence that Lateral MOSFET has lower THD than the vertical one. As IRFP ones are widely available, I would like to just stick with them.
2N5551/2N5104 and ZVN0124/ZVP4424 have the same pinout, and they are actually interchangeable throughout in my circuit. Q1, and Q2 can be changed to MOSFET, too.
That would be a full MOSFET amp.
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I would mount one of the MJE340 - 350 on the cooler. Then with changing R9 and R10 is it possible to get perfect thermal tracking for the idle current in Q5 and Q6. The bigger the resistor for the transistor on the cooler is the greater the thermal compensation will be. And R9 + R10 should stay about the same so it is possible to adjust the idle current to a correct value. The one that is not mounted on the cooler can of course be replaced by BC327 - 337 if that is easier for the layout.
If you put a diode connected (short B-C) BC327 in series with R5 and and a BC337 in series with R4 you will get the same current in the input pairs. I think that would decrease your distortion a bit. For me the equal current in the input transistors is of equal importance as the equal resistors for AC current. R5-R6 and R4-R7.
If you put a diode connected (short B-C) BC327 in series with R5 and and a BC337 in series with R4 you will get the same current in the input pairs. I think that would decrease your distortion a bit. For me the equal current in the input transistors is of equal importance as the equal resistors for AC current. R5-R6 and R4-R7.
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Right, 10uF would be a sensible choice in this schematic.
220uF is brought from a very early BJT version.
Yes, ideally MJE340-350 should be on the heatsink.
However, I am working with an existing chassis and heatsink, which has limited heatsink mounting area. I might have to extend the leads of MJE340/350 and stuck them in between the fins.
The topology is more a folded cascode than a current mirror. The current mirror portion would be bypassed by C6 and C7 at high frequency. The folded cascode portion remains active through out the bandwidth. Folded cascode requires the current of R4 and R5 to be greater than the current of input pair, to be functional.
My early prototype shows 8mV DC offset at the output. I think it is fine.
To me a cascode has a transistor for current gain and one with the base (gate) AC grounded and the signal from the current amplifier to the emitter (source) in order to get amplified voltage on the collector (drain).
In this case we have a signal to the Q12 drain and about the same but mirrored signal to the gate.
Which signal will now dominate? My opinion is that the current gain in Q12 is so big for normal frequencies that we have no reason at all to consider the signal into the drain. We also have no virtual ground on the gate which means that Q12 will behave about as a normal GE stage with 330 ohm to the rail.
Anyway if Q12 were a bipolar transistor we would have a linearizing effect because the base to emitter unlinearity in Q3 and Q12 will be about equal but opposite. With the MOS that falls away but it will anyway work better as the current gain is so much higher than in a bipolar.
Still it is a very interesting topic and the amplifier works well with simulated transistors.
I just wonder. The difference in gate voltage in the input pairs will cause difference in the current in Q12 and Q18. Will you do anything to keep that in the region or is the differencies to small to consider?
In this case we have a signal to the Q12 drain and about the same but mirrored signal to the gate.
Which signal will now dominate? My opinion is that the current gain in Q12 is so big for normal frequencies that we have no reason at all to consider the signal into the drain. We also have no virtual ground on the gate which means that Q12 will behave about as a normal GE stage with 330 ohm to the rail.
Anyway if Q12 were a bipolar transistor we would have a linearizing effect because the base to emitter unlinearity in Q3 and Q12 will be about equal but opposite. With the MOS that falls away but it will anyway work better as the current gain is so much higher than in a bipolar.
Still it is a very interesting topic and the amplifier works well with simulated transistors.
I just wonder. The difference in gate voltage in the input pairs will cause difference in the current in Q12 and Q18. Will you do anything to keep that in the region or is the differencies to small to consider?
Q3 and Q12 make a current mirror (an AC current mirror with fixed DC current offset). According to Wiki, it works like a feedback-assisted current mirror.
https://en.wikipedia.org/wiki/Current_mirror#Feedback-assisted_current_mirror
Unlike the traditional 3 stage amps, this amp only has one voltage gain stage. The voltage gain heavily relies on the output impedance of the VAS. The grounded folded cascode isn't good enough. This "feedback assisted current mirror" has about 10M Ohm output impedance. If the gm of the input stage is about 100mS. The gain is about 120 dB (open loop). With 26 dB close loop gain, it would end up >90dB NFB at DC.
Regarding the DC offset, anything less than 100mV is acceptable for me. My 1st prototype is with BJT input pair, I am going to test some mosfet input stage shortly.
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Latest iteration.
Had researched a little bit into DC offset.
There is DC offset cancellation mechanism going on. The criteria to achieve the cancellation is as following.
1. R4~R7=2x (R19 and R21)
2. The current of Q11 and Q14 is about the same current as Q3 and Q4.
With this, I only got 18mV DC offset without matching the input MOSFET.
Had researched a little bit into DC offset.
There is DC offset cancellation mechanism going on. The criteria to achieve the cancellation is as following.
1. R4~R7=2x (R19 and R21)
2. The current of Q11 and Q14 is about the same current as Q3 and Q4.
With this, I only got 18mV DC offset without matching the input MOSFET.