I've noticed in some schematics using MOSFETs that the p-type anf n-type output devices have different value gates-stopper resistors. I presume this is because that are few/no truly complimentary device pairs. Yet browsing datasheets and doing a search here it is far from clear to what determines the valur of the stoppers. Im only guessing but is it related to capacitance spec? And would one choose stopper values roughly proportionate to the difference between the two devices? I.e., if one of the paired devices has half the capacitance figure, does that translate to a stopper value half that of the other?
sam9 said:
I have always thought that the gate stoppers are there to prevent any (high frequency) oscillation. essentially the gate stopper prevents the gate to be charge up and discharge too fast. a larger stopper works better in that regard but worsen's high frequency performance. so it is sort of a compromise (like anything else)
The typical value for L-MOSFET is 470ohm (their cap capacitance is in the 1000pf range I think). For a typical Hexfet, it is twice that (1700nf would be a good starting point). so I use 220 or 110 ohm depending on what I have.
One exception is the 630/9630 pair from IRF. They have gate capacitance in line with the L-MOSFET. But they are pretty wimpy in terms of current capabilities so you kind of have to parrallel two of them to get the performance of one 540/9540, defeating the purpose of having them in the first place.
, otherwise it goes mad.
Thanks. That clarifies things a bit. That was my understanding regarding the need. What I wasn't clear on whether there was some specific calculation to determine the appropriate value or whether there are "typical" vlues that have evolved simply because they have been found to work.
Gate stoppers typical values
I'm sure one can calculate an optimum value for a gate resistor. For myself, it is usually done during prototyping.
As millwood suggested, 470 ohms is about right. if you lower this value too much, you will find that the parasitic capacitance of mosfets becomes problematic. With a scope, you will see funny waves riding on your fundamental (visible with 10K square at 5mV resolution). This is a sign of marginal instability. Conversely, using a value of say 1K will roll of the highs too much, thus dulling the amp.
I'm sure one can calculate an optimum value for a gate resistor. For myself, it is usually done during prototyping.
As millwood suggested, 470 ohms is about right. if you lower this value too much, you will find that the parasitic capacitance of mosfets becomes problematic. With a scope, you will see funny waves riding on your fundamental (visible with 10K square at 5mV resolution). This is a sign of marginal instability. Conversely, using a value of say 1K will roll of the highs too much, thus dulling the amp.
I know this is an old thread, however I have an answer to this, some expert corroboration would be good though. Please see
http://www4.head-fi.org/forums/showthread.php?t=82970
In this circuit the P-Channel IRF9z34n has a Ciss of 620 pF and the N-Channel IRFz24n a Ciss of 370 pF. In the interests of providing bandwidth symmetry the author quotes 2 solutions:
1) Since the difference is 250 pF, add a 220 pF (nearest standard value) between the N-Channels gate and source pins. Use a gate stopper resistor of 100 ohms on each gate.
2) Since the ratio of 620:370 is 1.67 use a gate stopper resistor on the N-channel gate 1.67 times larger than the P-channel and don't add the capacitor.
http://www4.head-fi.org/forums/showthread.php?t=82970
In this circuit the P-Channel IRF9z34n has a Ciss of 620 pF and the N-Channel IRFz24n a Ciss of 370 pF. In the interests of providing bandwidth symmetry the author quotes 2 solutions:
1) Since the difference is 250 pF, add a 220 pF (nearest standard value) between the N-Channels gate and source pins. Use a gate stopper resistor of 100 ohms on each gate.
2) Since the ratio of 620:370 is 1.67 use a gate stopper resistor on the N-channel gate 1.67 times larger than the P-channel and don't add the capacitor.
Nick Walker said:
Hi Nick
It is a coincidence that this thread comes up this time since I wanted to get comments from Erno Borbely this week on my latest design (based on the Hafler DH-200 so that is why I ask the designer itself of that amp) and one comment he had was to REMOVE the G-S capacitor on the N channel and put a 33pF between the G-D of the same N channel. I reminded him that there was a G-S capacitance in its DH-200 design and he replied that it was a mistake at that time. I could not get the reasoning of that change of cap location but when I check its design on his web site I notice that he uses only the small G-D cap now with same gate resistor value for both N and P channels. I tried that change but I could not notice if it was better or worse than with the G-S cap on the N channel.
Yes it is a compromise between stability and HF performance.
My Eidetic GB1b/2b power amplifiers used 3 paralleled pairs of Toshiba 2SK405/J115 per channel. When designing the PCB I positioned close mounted bypass caps right between/back from each pair and was able to ensure stability with 33ohm and 47 ohm gate resistors, according to their drive capacitance difference. There was no hint of HF oscillation.
It seems absurd to me to add capacitance to degrade one to match the C of the other, when what we want to match is the speed. Then slow them both with stoppers. Why design low Z drive for MOSFETS only to swamp it with oversize stoppers and Clag. that's C lag.
My Eidetic GB1b/2b power amplifiers used 3 paralleled pairs of Toshiba 2SK405/J115 per channel. When designing the PCB I positioned close mounted bypass caps right between/back from each pair and was able to ensure stability with 33ohm and 47 ohm gate resistors, according to their drive capacitance difference. There was no hint of HF oscillation.
It seems absurd to me to add capacitance to degrade one to match the C of the other, when what we want to match is the speed. Then slow them both with stoppers. Why design low Z drive for MOSFETS only to swamp it with oversize stoppers and Clag. that's C lag.
hi,
my understanding on gatestopper resistors is just like designing
a low pass filter at around 350khz.....
f(khz)= 1 / (2piRC)
were: f= frequency in khz
R = gatestopper resistor
C= mosfet input capacitance
somebody correct me if I'm wrong
regards,
hienrich
my understanding on gatestopper resistors is just like designing
a low pass filter at around 350khz.....
f(khz)= 1 / (2piRC)
were: f= frequency in khz
R = gatestopper resistor
C= mosfet input capacitance
somebody correct me if I'm wrong
regards,
hienrich
Hi Hienrich,
I think the equation you have devised for the gate resistors to act as low pass -filter doesnot holds good when you would came accross practical real world drive of high frequency into reactive loads especially and there may arise asituation when the both upper and lower mosfets starts to crossconduct each other....
Truly speaking when paralleling mosfets this doesnot hold good in real life encounters...
Kanwar
I think the equation you have devised for the gate resistors to act as low pass -filter doesnot holds good when you would came accross practical real world drive of high frequency into reactive loads especially and there may arise asituation when the both upper and lower mosfets starts to crossconduct each other....
Truly speaking when paralleling mosfets this doesnot hold good in real life encounters...
Kanwar
Ultima Thule,
Eidetic was the Australian brand of amplifier I produced ( and took over the market) in Australia in 1989-1994. These were landmark performance products and swamped the performance of the big overpriced muncho amps available.
Unfortunately, I had to terminate production after threats against my young family.
Eidetic was the Australian brand of amplifier I produced ( and took over the market) in Australia in 1989-1994. These were landmark performance products and swamped the performance of the big overpriced muncho amps available.
Unfortunately, I had to terminate production after threats against my young family.
kanwar:
yo! I know this was not a real fact , actually I've just refered
to a circuit I've encountered and tried for myself calculating,
the results were close to each others RC time constants using
BUZ901DP's and BUZ906DP's Lateral Mosfets Ciss...
but is there an optimum ot other way to do this.?
rgrds,
macweb
😎
yo! I know this was not a real fact , actually I've just refered
to a circuit I've encountered and tried for myself calculating,
the results were close to each others RC time constants using
BUZ901DP's and BUZ906DP's Lateral Mosfets Ciss...
but is there an optimum ot other way to do this.?
rgrds,
macweb
😎
amplifierguru said:
Oh my GOD , I thought i was the only one on the earth with this type of situation alone.... but we havenot stopped the production in our case .... when we were new in this business ,one of our competitor's tried to threat us and what we did is something to hear... we [me, my partner , my father & lots of friends with hot blood rising up the head]simply get to his place and RamSHACKEd his house and turned down his workshop into junkyard and ofcourse force biased that guy in to thermal runaway in his bathtub and that too in legal way .....and till present that guy never showed up....thats the way we treat the fellows who mistreat with us.....He used to say"either stop your businesss or you have to face the dire consequences in both personal and professional matters" we simply showed him up what type of dire consequences he has to face .....by mistreating with us...
I really get shocked to hear about the threat to your family...
hienrich said:
YEs there is an optimum way exist by which one could calculate the gate resistors value... and thats in the application note of both IRF & APT ....check them out.
Workhorse,
I have used 220 Ohm for IRFP240/9240.
But now I want to use IRF610/9610 ...
Would 100 Ohm be a good value for the IRF610/9610?
I have used 220 Ohm for IRFP240/9240.
But now I want to use IRF610/9610 ...
Would 100 Ohm be a good value for the IRF610/9610?
Consider placing a zero ~30MHz (Zobel filter) from gate to drain as close to the device leads as possible and you will be able to reduce the gate stopper. This will increase the Fc of the LP filter created by the gate stopper and the input capacitance while still being able to critically dampen the oscillator created by the mosfet internal components.😉
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