Is Dead-Time a Non-Issue with Half-Bridge P-N Pair?

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P-ch and N-ch MOSFETs, compared at same Vds and Rds-on level, don't have the same Vgs-th, not same capacitances, not same transconductance, so gate drive has to be adjusted differently, in turn corresponding to "dead time adjustment". With 2x N-ch MOSFET dead time adjustment it is more commonly achieved by adjusting timing of a logic signal with logic gates and R-C-D stages. There is no way to escape from the dead time optimization step (without escaping from audio quality).
 
I understand your question such that If you used an NPN-PNP push-pull stage (base terminals connected to one another) and drove the two bipolar transistors into saturation (high <> low) dead-time and conduction overlap would not be an issue such as with FETs.
The starting up current of one bipolar would help removing the minority carriers from the other and switch it off.
The problem with bipolars is poor saturation, less fast switching an a more complex and inefficient drive circuit needing boot-strapping.

I'm not that good with semiconductor physics.
 
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