I'm using LTSpice to optimize a VI limiter that I'd like to make an optional feature in a design. What I'm looking for is a way to introduce a readily definable reactance into the load so I can plot the protection locus while stepping values.
I don't really want a simulated speaker, those I have seen. I'm just looking for the easiest / preferred way to simulate a load that is reactive. Suggestions? I'm sure the answer is likely simpler than I think. Thanks for any ideas offered.
I don't really want a simulated speaker, those I have seen. I'm just looking for the easiest / preferred way to simulate a load that is reactive. Suggestions? I'm sure the answer is likely simpler than I think. Thanks for any ideas offered.
stepping the values of L and C is one way
you can add a current source loading the output with a sine (or multisine) with phase different from the input signal - equivalently you can put a Vsource with the different phase in series with the load R
behavioral sources can take a Laplace equation - but there are issues with discretization/frequency range and time step size that make it a expert level technique
you can add a current source loading the output with a sine (or multisine) with phase different from the input signal - equivalently you can put a Vsource with the different phase in series with the load R
behavioral sources can take a Laplace equation - but there are issues with discretization/frequency range and time step size that make it a expert level technique
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Thanks for the suggestions jcx.
I had a look at Bob Cordell's book and there is a really small section on current limit and SOA testing in LTSpice. As suggested in his text I ended up just setting my resistance and used a simple series capacitor to add reactance. I chose this since capacitive reactance is considered the more problematic (current leading voltage) for an audio amplifier.
Below is the schematic and plot. I drew on the SOA 'curve' from the data sheet manually. I just need to step values to look at different levels of reactive loading.
I'm always open to other simple sanity checks as well.
I had a look at Bob Cordell's book and there is a really small section on current limit and SOA testing in LTSpice. As suggested in his text I ended up just setting my resistance and used a simple series capacitor to add reactance. I chose this since capacitive reactance is considered the more problematic (current leading voltage) for an audio amplifier.
Below is the schematic and plot. I drew on the SOA 'curve' from the data sheet manually. I just need to step values to look at different levels of reactive loading.
I'm always open to other simple sanity checks as well.
Attachments
Bob's book at pp's 322 & 323, Fig 15.7 show the general case for all reactive loads of the same minimum impedance.
FWIW, I don't think your VI limiter resistor values are optimal.
Brian.
FWIW, I don't think your VI limiter resistor values are optimal.
Brian.
The very reason I want to properly simulate the scenario where the VI limiter would activate is to optimize the values.
From the information I have read, it appears that the 'all instances' scenario can be covered by the minimum expected resistance and twice the intended operating voltage. Would it be reasonable in simulation to just test into a resistive load at double the design voltage?
I need to correct myself, the simulation would be at twice the minimum impedance and twice the design voltage to represent an 'all cases' simulation. That is assuming I have it straight in my head...
I’m not sure if driving 2xRe to 2x Vsupply equates to the stress of driving a reactive load. It doesn’t seem like it to me. Perhaps this is a question for Mr Cordell.
I don’t use Spice to analyse VI limiters because I’ve never seen it done satisfactorily. I use my own spreadsheet to plot the necessary data (linear SOA curve, reactive load boundary and VI locus) onto a linear graph using Excel.
I’ve read that 4Ω@±60 is considered a reasonably arduous reactive load to satisfy high power amplifier pretentions (e.g. 2Ω + 46uF in series at 1kHz, if my maths is correct). Therefore I use 2Ω as my Re when constructing the negative boundary slope on the Ic/Vce SOA graph. This must lie behind the VI locus, which in turn lies behind the derated SOA curve.
If you haven’t already, I suggest you look at Michael Kiwanuka’s paper on VI limiters, accessible from Bonsai’s site.
Brian.
PS Why doesn't this text editor accept micro and angle symbols???
I don’t use Spice to analyse VI limiters because I’ve never seen it done satisfactorily. I use my own spreadsheet to plot the necessary data (linear SOA curve, reactive load boundary and VI locus) onto a linear graph using Excel.
I’ve read that 4Ω@±60 is considered a reasonably arduous reactive load to satisfy high power amplifier pretentions (e.g. 2Ω + 46uF in series at 1kHz, if my maths is correct). Therefore I use 2Ω as my Re when constructing the negative boundary slope on the Ic/Vce SOA graph. This must lie behind the VI locus, which in turn lies behind the derated SOA curve.
If you haven’t already, I suggest you look at Michael Kiwanuka’s paper on VI limiters, accessible from Bonsai’s site.
Brian.
PS Why doesn't this text editor accept micro and angle symbols???
lower case mu: µµµµµµµµµµµµµµµµµµµµµµµµµµµµ
angle: ∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠
Works for me. As a last resort you can simply copy and paste from the above.
angle: ∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠
Works for me. As a last resort you can simply copy and paste from the above.
My post was written in a word doc. with the (angle) and (mu) symbols, but they changed once pasted into the message pane.
But pasting from your post looks o.k.???
µµµµµµµµµµµµµµµµµµµµµµµµµµµµ
∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠
But pasting from your post looks o.k.???
µµµµµµµµµµµµµµµµµµµµµµµµµµµµ
∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠∠
When looking at many SOA curves they are presented in Log-Log format, but plotting on Lin-Lin is shown for many SOA locus calculations.
I can easily plot the current limited and power limited parts of the curve on linear axes mathematically, but how does one plot with reasonable accuracy the second breakdown area? It seemed easy enough to basically draw on the manufacturers data on a Log-Log plot as the lines are straight, but on linear axes I'm not sure how to plot the curve.
I can easily plot the current limited and power limited parts of the curve on linear axes mathematically, but how does one plot with reasonable accuracy the second breakdown area? It seemed easy enough to basically draw on the manufacturers data on a Log-Log plot as the lines are straight, but on linear axes I'm not sure how to plot the curve.
Determining a VI locus from the log-log graph is nigh impossible; it must be converted to lin-lin. The maths to do this is as follows.
General form equation for the Ic/Vce log-log slope is Ic=k(Vce)^n
n = (logy1-logy2)/(logx1-logx2)
k = y1/(x1)^n
x1,y1 and x2,y2 are the start and end co-ordinates of the slope respectively.
Thus a table (I use Excel) of Vce against Ic can be generated, and from that a curve can be automatically plotted.
(For constant power law Ic=P/Vce = P(Vce)^-1 so k = P & n = -1)
Be aware, though, that many power BJT’s have a power slope that does NOT follow the law P = VI, For example, look at the ONSemi MJL3281 datasheet. For the 1 sec profile, it starts at Ic ~ 15A (y1), Vce ~ 17.3V (x1) (i.e.~260W), and ends at 1.8A (y2), 78V (x2) (~140W) . So after entering those values in the above equations, the factor n equates to -1.4, not -1 as the power law would suggest (and k ~ 820). So a simple Ic = P/Vce doesn’t work for that device; it won’t produce a linear SOA curve that reflects the log-log slope. The equation to use would be Ic = 820(Vce)^-1.4
So it’s worth a thought. The average power over the slope is 200W, as the data sheet says, but from about 33V, well inside 2nd breakdown, it gradually becomes a lot less.
The few Japanese devices I’ve plotted follow the constant power law faithfully, as does the MJL4302, (and MOSFETS) but some common power BJT’s don’t.
I’m still hoping that some guru can come up with an LTspice method for this.
Hope this helps.
Brian.
General form equation for the Ic/Vce log-log slope is Ic=k(Vce)^n
n = (logy1-logy2)/(logx1-logx2)
k = y1/(x1)^n
x1,y1 and x2,y2 are the start and end co-ordinates of the slope respectively.
Thus a table (I use Excel) of Vce against Ic can be generated, and from that a curve can be automatically plotted.
(For constant power law Ic=P/Vce = P(Vce)^-1 so k = P & n = -1)
Be aware, though, that many power BJT’s have a power slope that does NOT follow the law P = VI, For example, look at the ONSemi MJL3281 datasheet. For the 1 sec profile, it starts at Ic ~ 15A (y1), Vce ~ 17.3V (x1) (i.e.~260W), and ends at 1.8A (y2), 78V (x2) (~140W) . So after entering those values in the above equations, the factor n equates to -1.4, not -1 as the power law would suggest (and k ~ 820). So a simple Ic = P/Vce doesn’t work for that device; it won’t produce a linear SOA curve that reflects the log-log slope. The equation to use would be Ic = 820(Vce)^-1.4
So it’s worth a thought. The average power over the slope is 200W, as the data sheet says, but from about 33V, well inside 2nd breakdown, it gradually becomes a lot less.
The few Japanese devices I’ve plotted follow the constant power law faithfully, as does the MJL4302, (and MOSFETS) but some common power BJT’s don’t.
I’m still hoping that some guru can come up with an LTspice method for this.
Hope this helps.
Brian.
Thanks for that information. I will take some time to get that worked out for myself.
You also confirmed what I noticed about the 'power limited' part of the manufacturers graph not actually matching a 200W curve.
You also confirmed what I noticed about the 'power limited' part of the manufacturers graph not actually matching a 200W curve.
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