I want to use an usb to i2s board ( cm 6631A ) that output lrck and sck but not bck , can i use sck as bck in simultaneous mode for the tda 1541 A , with no oversampling ?
Thanks in advance for your help
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Thanks in advance for your help
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Typically the I2S bit clock is named bck (bit clock) or sck (serial clock). Word clock is lrck (left-right clock) or ws (word select). SoC I2S interfaces often feature master clock (mck) from which the other clocks are divided, codecs often need that clock too.
The sck on my board is 128 fs , normaly bck is 64 fs , so they do not have the same rate , will the tda1541a work with 128 fs in simultaneous mode ?
it is very close to its max frequency from datasheet ( 6.4 mhz )
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it is very close to its max frequency from datasheet ( 6.4 mhz )
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CM6631 has non-standard BCK output as it is 128fs for 44k1/48k and 64fs for higher sample rates. Modern DAC chips can work with 128fs but I doubt if TDA1541 can. You need to try it to find out. You could add a div/2 on BCLK if 128fs does not work.
Is even 64fs compatible with TDA1541? Since it's an old 16bit DAC, does it not expect 32bit frame and 32fs bitclock?
Fact is it doesn't work at 128 fs , and the i2s to simultaneous glue logic ( same as the ryanj board ) has some reduction , so I have to find and usb to i2s board that output bck at 64 fs or divide by 2 the actual 128 fs
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Older 16bit devices typically support 32Fs, 48Fs and 64Fs. 128Fs is new, and frankly unnecessary, though I suspect its a compromize for chips without MCLK (the fastest clock sets the jitter performance)?
question is , what is the best solution for that job , any d flip flop will do ? , or there is any other good solutions ?
any input welcome 😉
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any input welcome 😉
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For div/2 single gate flip flop (e.g. 74lvc1g80) works fine. For div/4 binary counter (e.g. 74lvc163) is easiest. In addition it may be beneficial to reclock LRCK (or WS) with a flip flop.
I don't doubt it can be added and I don't doubt that there will be a sound output of some kind. I just don't think the sound will be what the artist intended.
Hard to say without seeing how I2S signals look on scope or analyzer. Presumably this card with 128fs BCK at 44k1/48k works with some dacs so frame size is likely still 64 bits.
ok , what could go wrong when you divide by two the frequency of bit clock , a far as the signal doesn't become jittered or noisy in any kind , the i2s to simultaneous glue logic has 14 chips along the path , would one more chip degrade the signal that much ??
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If the timings are as in post #17 (i.e. SDATA as in 3rd row) BCK divided by two would miss every other data bit.