Hi all,
Building a DAC using Texas Instruments DIR9001 for the SPDIF to I2S stage. Two questions around SPDIF in general.
1. the datasheet quotes a low 50ps jitter. For all these super duper async USB chips none appear to publish jitter specification. Will they beat 50ps?
2. Second, both the DIR9001 and subsequent stages will share ground with the input source. SPDIF (non optical) tends to use an isolating transformer and the only reason I can see is to avoid a ground loop, however this is a digital stage and I don't see it as being applicable? I'm wondering if I can do a straight connection.
3. A few other input circuits use two inverters to boost the COAX to TTL level. I'm wondering why the need for the filter, why not use a single op-amp?
Building a DAC using Texas Instruments DIR9001 for the SPDIF to I2S stage. Two questions around SPDIF in general.
1. the datasheet quotes a low 50ps jitter. For all these super duper async USB chips none appear to publish jitter specification. Will they beat 50ps?
2. Second, both the DIR9001 and subsequent stages will share ground with the input source. SPDIF (non optical) tends to use an isolating transformer and the only reason I can see is to avoid a ground loop, however this is a digital stage and I don't see it as being applicable? I'm wondering if I can do a straight connection.
3. A few other input circuits use two inverters to boost the COAX to TTL level. I'm wondering why the need for the filter, why not use a single op-amp?
Attachments
Ad 1) Proper USB async does not use PLL, a precise clock is used for reading samples from the internal FIFO. Theoretically it can have less jitter than the PLLed clock from the SPDIF receiver.
Ad 2) The ground loop does not affect the digital path indeed. But the digital circuits share ground with the subsequent analog section where the ground loop through the digital section can have an impact. Isolating digital path is way easier than the analog one, that's why the optical cables, isolation transformers etc.
Ad 3) That circuit is a waveform shaper and level shifter. Why opamps in the digital circuits?
Ad 2) The ground loop does not affect the digital path indeed. But the digital circuits share ground with the subsequent analog section where the ground loop through the digital section can have an impact. Isolating digital path is way easier than the analog one, that's why the optical cables, isolation transformers etc.
Ad 3) That circuit is a waveform shaper and level shifter. Why opamps in the digital circuits?
With well designed async USB interface, jitter seen by DAC, depends of oscillator's (located close ot DAC) jitter only and nothing else.
And is not a trivial task to find the oscillator with so bad jitter as 50ps 🙂
HC04 is a digital circuit but its being biassed by the feedback R into an analog operating mode.
1.That 50ps. figure is only the intrinsic jitter of the receiver's clock. So, if you were to input an SPDIF signal with zero jitter, the signal recovered jitter would be 50ps. Which means, that the recovered signal jitter can never be lower than the intrinsic jitter of the receiver clock. However, SPDIF signals recovered by the DAC typically have much more jitter than the intrinsic jitter of most SPDIF input receiver circuits. The much more challenging task for an input receiver is to suppress the jitter that's already present on the SPDIF signal.
2. Ground-loop noise interruption across an SPDIF link has two benefits. One, is that ground-noise can contaminate the DAC's local oscillator and increase it's intrinsic jitter. The other is that in can also contaminate the DAC's analog circuits, such as the I/V, and the active filter/output amplifiers.
Hi Ken,
1. I believe that's what the DIR9001 is doing. It's not recovering the clock from the signal. Texas Instruments say it's 50ps and I'll inclined to believe them, whereas I haven't seen any of the USB Async solutions provide any evidence to indicate they can beat this. Tried Google as well and nothing has come up.
2. Even if the SPDIF is isolated the source (computer) will be providing the power for the rest of it, so the ground isn't isolated. As such I can't see any benefit.
--
Realised yesterday just how fast the inverters are in comparison to most op-amps, operating at up to 300MHz. IIRC the spdif is ~1-3MHz and cheaper op-amps won't keep up.
1. I believe that's what the DIR9001 is doing. It's not recovering the clock from the signal. Texas Instruments say it's 50ps and I'll inclined to believe them, whereas I haven't seen any of the USB Async solutions provide any evidence to indicate they can beat this. Tried Google as well and nothing has come up.
2. Even if the SPDIF is isolated the source (computer) will be providing the power for the rest of it, so the ground isn't isolated. As such I can't see any benefit.
--
Realised yesterday just how fast the inverters are in comparison to most op-amps, operating at up to 300MHz. IIRC the spdif is ~1-3MHz and cheaper op-amps won't keep up.
Hi Snoop,
So long as the transport is the flow master, meaning, it contains a free running clock generator, the transmitted SPDIF signal embeds the clock together with the data on a common biphase digital signal. The clock and data then must be separated at the DAC, which requires some form of PLL implementation. PLLs inherently open a window for lower frequency jitter to enter to DAC. I guarantee you, that the DIR9001 can not recover a 50ps. jitter clock no matter the jitter on a (non-synchronized) SPDIF signal.
Why would the source be powering the SPDIF reciever circuit located in the DAC? Perhaps, you are confusing this with powering a USB reciever?
Last edited:
SPDIF receiver runs in two modes: (A) locked to the internal clock if no input SPDIF signal is present or (B) locked to PLL-recovered clock from the incoming SPDIF signal.
Actually powering your analog circuits from the computer is where the ground loop matters a lot. There will be currents between the SPDIF ground and the power supply ground flowing through your motherboard ground planes, and part of them will flow through the SPDIF -> DAC -> amp ground lines, unless balanced connection between the DAC and the amp is used. Look at Adding an Amp into Thin-Client PC
Yes the DAC only has balanced outputs.
DIR9001 -
Low-Jitter Recovered System Clock: 50 ps
Jitter Tolerance Compliant With IEC60958-3
DIR9001 -
Low-Jitter Recovered System Clock: 50 ps
Jitter Tolerance Compliant With IEC60958-3
I'll try to explain:
For SDM DAC only MCLK jitter is important (except ESS in async. mode).
For old parallel DAC, LRCLK jitter is important, which can be solved by re-clock (using flip-flop) from MCLK.
So using good oscillator close to the DAC chip, jitter will depends only of this oscillator.
It's signal also clocks USB-chip (usually through the buffer, jitter of this signal is not important).
If opposite, oscillator is close to USB-chip, is worth, but acceptable.
But - only if there are no galvanic isolators.
If oscillator's signal goes to the DAC through galvanic isolation, the jitter will be much worse.
For SDM DAC only MCLK jitter is important (except ESS in async. mode).
For old parallel DAC, LRCLK jitter is important, which can be solved by re-clock (using flip-flop) from MCLK.
So using good oscillator close to the DAC chip, jitter will depends only of this oscillator.
It's signal also clocks USB-chip (usually through the buffer, jitter of this signal is not important).
If opposite, oscillator is close to USB-chip, is worth, but acceptable.
But - only if there are no galvanic isolators.
If oscillator's signal goes to the DAC through galvanic isolation, the jitter will be much worse.
Another option is to draw the signal from PCI-E directly with a CM8888. I've began that conversation with CMedia but I don't have high hopes. My assumption is anything being converted adds jitter.
I'm aware that a good ASYNC USB method should have next to no jitter, I think that's what you are saying, the jitter is based on the oscillator, whereas for SPDIF it's based on the oscillator and how close it can PPL the original clock.
I'm aware that a good ASYNC USB method should have next to no jitter, I think that's what you are saying, the jitter is based on the oscillator, whereas for SPDIF it's based on the oscillator and how close it can PPL the original clock.
What makes you think that jitter does not depend on MCLK in ESS async mode? AFAIK jitter performance is solely dependant on MCLK for ESS chips regardless of their operating mode, wether with DPLL or DPLL off (synchronous mode).