Symamp – simple complementary-symmetrical amplifier
I have decided to design and build a sample of complementary-symmetrical amplifier that should be:
THD is not a goal here, as nonlinear distortion below 0.1% is barely audible and if yes, than only with a sine tone at certain level. Not with music.
So, this is the circuit schematics.
T1-T4, Q1-Q4 make the complementary-differential pairs loaded by current mirrors. Q5, Q6 and T5,T6 make a folded cascode VAS. Folded cascode is important to keep VAS current stability vs. input offset voltage. It works very well. Q10, Q11 and T20, T30 make a conventional 2EF output stage.
Loop gain stability margin is 62° and the circuit is stable even with the capacitive load, without the need to use an output coil.
I have built and measured a functional sample. The PCB is too large for the reason it must fit to my pre-drilled prototype amplifier case. The PCB is carefully designed with respect to signal grounds, please note very low level of mains related components in the measurements below.
Measurements
I have decided to design and build a sample of complementary-symmetrical amplifier that should be:
- simple
- reliable
- stable
- easy to build
- with sufficient parameters
- 2x50W/4ohm at 1% THD
THD is not a goal here, as nonlinear distortion below 0.1% is barely audible and if yes, than only with a sine tone at certain level. Not with music.
So, this is the circuit schematics.
T1-T4, Q1-Q4 make the complementary-differential pairs loaded by current mirrors. Q5, Q6 and T5,T6 make a folded cascode VAS. Folded cascode is important to keep VAS current stability vs. input offset voltage. It works very well. Q10, Q11 and T20, T30 make a conventional 2EF output stage.
Loop gain stability margin is 62° and the circuit is stable even with the capacitive load, without the need to use an output coil.
I have built and measured a functional sample. The PCB is too large for the reason it must fit to my pre-drilled prototype amplifier case. The PCB is carefully designed with respect to signal grounds, please note very low level of mains related components in the measurements below.
Measurements
Well - yes. Just good, built, verified, stable, without oscillations, very good temperature stability and no unwanted surprises for the builders. And, the simulation fits to the real world results, as there are no circuit tricks used.
This is a 10kHz square wave response into 4ohm//100nF load. Please note there is no output coil used and the amp is still stable with this load.
The gain is low comparing to a traditional LTP with current mirror. I see there is negative feedback around the input stage. Make it essentially a cascode VAS. That's why you set the degenerate resistors to 0 from the input stage to make up the gain.
PS: I checked again. Based on the circuit. The VAS is about 10x current gain over the input stage. It is better than a vanilla folded cascode VAS about 20dB gain.
PS: I checked again. Based on the circuit. The VAS is about 10x current gain over the input stage. It is better than a vanilla folded cascode VAS about 20dB gain.
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Yes I needed more gain. The folded cascode is used for the reason of VAS current stability. If it is not used, even 1mV offset change makes the VAS current accelerate to universe. As of now with folded cascode, it is perfectly stable. VAS current is 10mA.
I have a lot of experience with folded cascode designs, the first one was in 2009 and of course you will find it here at diyaudio as well.
https://pmacura.cz/dispre2_en.htm
It is always good to see a built and tested amplifier. 🙂
The use of local feedback to limit the gain of the differential pair avoids the usual pitfall in this kind of amplifier. You get an "A" for a successful design.
Ed
The use of local feedback to limit the gain of the differential pair avoids the usual pitfall in this kind of amplifier. You get an "A" for a successful design.
Ed
Applying Solomon (non cascode) analysis by eyeball, suggests GBWP=30MHz and SR=10V/usec ; are either of these close to correct?
SR should be right. I am not sure the bandwidth.
From the bode plot from OP, the bandwidth seems low for the gm=1ma/27. I suspect the LTP is actually working in one arm. Only half of input current could be used to charge miller cap.
So half of 30MHz would be 15MHz. 21 times close loop gain, then you get 700KHz from the bode plot in the OP.
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I get 10V/us and 15MHz. The differential pair has half the gm of a single transistor. Having two amplifiers in parallel makes up for the halving when adding currents but not when adding voltages.
Ed
Ed
The LTP is almost perfectly balanced, simulated and confirmed by measurements. Do not forget where the cascode current flows.
You guys guess too much😉.
The amp is able to handle difficult loads quite well, without a big penalty compared to 4ohm (I do not test 8ohm as speakers go much lower). Below some plots with 2.5 ohm load.
The amp must be stable and rugged.
P.S.: SR is not very high, but enough for audio and for this low power amplifier. You can see no problems at THD/20kHz/BW90kHz plots. SR could be higher if compensation caps are made lower. But why? It results only in worse stability and less immunity to capacitive load. I do not like chasing numbers for numbers.
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The amplifier works in reality with acceptable data.
Not much to question this.
Not much to question this.
Could you simulate it with traditional vas and make bode plot? I know it will blow up vas in reality, but it does no harm in simulation. Just make sure the VAS got some current. If it results twice the loop gain bandwidth, that means your original VAS only works on single end of the ltp.
Sorry to spoil your party, but Q12 is not a (risky) symmetrical diamont Vbe multiplier.
I like sym designs very much nonetheless.
I like sym designs very much nonetheless.
Nice work, Pavel.
But could me gives some questions.
1. Does such a curved differential pair load give better linearity than a symmetrical current mirror such as the one in your previous design?
2. Why You don't use Locanthi triple as output stages configuration?
But could me gives some questions.
1. Does such a curved differential pair load give better linearity than a symmetrical current mirror such as the one in your previous design?
2. Why You don't use Locanthi triple as output stages configuration?
The 100 us SOA of most output transistors is pretty square. Dissipations that short lived at very low impedance won’t kill them like the same impedance at 100 or 20 Hz will. You just have to make sure you don’t run out of beta. It is clipping a little sooner at 10K, likely quasi-saturation in the drivers (probably outputs too, but that can’t be helped short of paralleling). Those types were intended for higher voltage rails where you probably won’t get to within 5 volts of the rail anyway. HF performance would likely be a bit better sticking a TO-92 pair in front of them. For low voltage use I might be opting for the tired old BD139/40 drivers if the triple option is considered risky. Nobody seems to like them because they are dinosaur technology and don’t have any bling factor, but they work. If making a PCB for generic use, you might want to make them flippable to go TO-220/126.
SOA can be reliably simulated with a speaker (Rs + Ls) + ( Rr//Cr//Lr), resonant circuit in series with voice coil parameters. Here the low 2 x 25V and quite robust transistors are an advantage. During the last 20 years, I used more than 100 pairs of MJL3281/1302 and MJL21193/4 and never, never experienced a single failure.