Why is THD decreasing with increasing of load resistance? Is that because of higher voltage on load? Then Av is smaller, but circuit is more stabilized - THD is smaller? Sorry if i am talking **** 🙂
Can somebody explain me this in sentence or two?
I have also few other questions:
I measured rise time of my AB class amplifier and it gets shorter with increased output signal. Why is that?
this is a scheme - 500 mW 3 Transistors Audio Amplifier - HQEW.net
thank you very much!
Can somebody explain me this in sentence or two?
I have also few other questions:
I measured rise time of my AB class amplifier and it gets shorter with increased output signal. Why is that?
this is a scheme - 500 mW 3 Transistors Audio Amplifier - HQEW.net
thank you very much!
Hello martinho,
That's normal, with higher loads the THD is lower and with lower loads THD is higher, that's because the output devices have to supply more current and are afected by beta droop. The clipping also occurs earlier, if you only have two output devices you should be careful while trying to drive 4 ohm loads, you can destroy the devices by secondary breakdown if they have more current that they should have for that VCE.
PS: Strange circuit it only have VAS without CCS or bootstrapping and no differential IPS or Miller compensation, curious topology, where half voltage at the output is set.
This design is really stable it doesn't need a Zobel network.
Best regards,
Daniel Almeida
That's normal, with higher loads the THD is lower and with lower loads THD is higher, that's because the output devices have to supply more current and are afected by beta droop. The clipping also occurs earlier, if you only have two output devices you should be careful while trying to drive 4 ohm loads, you can destroy the devices by secondary breakdown if they have more current that they should have for that VCE.
PS: Strange circuit it only have VAS without CCS or bootstrapping and no differential IPS or Miller compensation, curious topology, where half voltage at the output is set.
This design is really stable it doesn't need a Zobel network.
Best regards,
Daniel Almeida
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Hi Daniel
Thanks on answer. Yeah, the circuit is really easy one, i am beginner, dont wanna complicate 🙂
So, why are they affected by beta drop? Is that because of less voltage on Load, so more voltage is on transistor and it goes to saturation causing beta drop? Its how i imagined, is that true? 🙂
Thanks on answer. Yeah, the circuit is really easy one, i am beginner, dont wanna complicate 🙂
So, why are they affected by beta drop? Is that because of less voltage on Load, so more voltage is on transistor and it goes to saturation causing beta drop? Its how i imagined, is that true? 🙂
Hi martinho,
Beta droop is caused by the raise of collector current, when the collector current raises, the current gain (beta) lowers, and the output stage will have a non linear behaviour. The transistor saturates earlier, because the Vce is higher for higher currents, for example it can saturate at Vce = 2 V for a 4 ohm load and at Vce = 1 V for a 8 ohm load.
Beta droop is caused by the raise of collector current, when the collector current raises, the current gain (beta) lowers, and the output stage will have a non linear behaviour. The transistor saturates earlier, because the Vce is higher for higher currents, for example it can saturate at Vce = 2 V for a 4 ohm load and at Vce = 1 V for a 8 ohm load.
Just about every transistor datasheet has a graph of collector current versus hfe (a.k.a. beta). One of the best transistor families in this regard is the MJL1302 and MJL3281, which is why it is loved by amp designers all over the world. Compare this with the MJ802 and MJ4502, which are also highly regarded but of an older generation, and you will see what is meant by beta droop. 🙂
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I disagree, I don't think beta droop is the whole story and with other circuit designs where the output devices have adequate drive signal you will still see increase THD with lower load resistance because the current swing is higher. A higher current swing means more of the I-V curve of the device is being exploited and since it is an exponential curve it gets more non-linear.
In order to understand the problem, one needs to look at output stage linearity and what happens when the output stage drives a load at various DC levels. In a nutshell, output stage output impedance is not constant, and since it forms a voltage divider with the load, voltage at the load is distorted accordingly. While the effect is greatly reduced by feedback, the output stage remains the dominating source for distortion in most amplifiers.
So why is output impedance not constant?
First off, we need to remember how output impedance of an emitter follower varies with collector current:
r_out = R_E || ( (r_be + R_source) / beta )
Now usually r_out is much smaller than our load, so the "R_E ||" part is negligible. The most important conclusion from the rest is:
r_out ~ 1 / beta
And then we may remember that transistor datasheets typically contain a plot of beta vs. collector current Ic. There's sort of a plateau at medium currents, with a gentler dropoff at very low currents and a quick one at very high ones. The latter is "beta droop". (Both effects are less pronounced in good transistors.) With lower beta comes higher r_out.
Back to our output stage. Let's use the common class AB push-pull type, start at midpoint (0 V output) and go up:
1. At first we are seeing idle current flowing through both transistors, and virtually no current flows into the load. Small signal wise, both transistors are now driving the load in parallel.
2. As voltage rises, the bottom transistor turns off and only the top one drives the load.
3. As voltage rises further, we may or may not reach the kind of currents needed to exhibit beta droop. If we do, output impedance increases, and output voltage suffers. Lower-impedance loads mean more current, hence more severe beta droop.
Now let's look at phases 1. and 2. again and distinguish two interesting cases:
a) Very low idle current. Now beta at midpoint becomes very low, r_out shoots up and relative signal level at the load drops off like a rock. You're getting sort of a "notch" on the middle. At no idle current at all (pure Class B), this "notch" potentially extends up to plus or minus one V_be, i.e. up to about +/-0.6 V. Very nasty crossover distortion results.
b) Rather high idle current, enough to reach that beta "plateau". Now the output impedance at midpoint (where both transistors are operating) is only half as high as further up or down (where only one transistor operates), and you see a gentle "bump" in signal levels there. This effect is referred to as "gm doubling". If it extends to the entire output amplitude, we are looking at Class A operation (which is defined by neither transistor ever turning off).
In practice, you'll be trying to choose idle current such that both of these effects just about cancel out, which gives minimum distortion at high output levels (even if the midpoint region does remain somewhat uneven). Another school argues that lower levels are more common in practice, and prefers "fat" AB operation with a low-distortion "gm doubled" (Class A) zone extending as far as normal volumes will demand, an approach that also has its merits even if distortion at higher levels is substantially worse. (Pure Class A operation in a decent-sized loudspeaker amp tends to require substantial power supplies and cooling, aside from being heavy on the power bill.)
Note that yet again, the severity of these two effects worsens with lower load impedance.
Douglas Self has a nice discussion of output stage linearity in his power amplifier book, with plots and all for various types.
So why is output impedance not constant?
First off, we need to remember how output impedance of an emitter follower varies with collector current:
r_out = R_E || ( (r_be + R_source) / beta )
Now usually r_out is much smaller than our load, so the "R_E ||" part is negligible. The most important conclusion from the rest is:
r_out ~ 1 / beta
And then we may remember that transistor datasheets typically contain a plot of beta vs. collector current Ic. There's sort of a plateau at medium currents, with a gentler dropoff at very low currents and a quick one at very high ones. The latter is "beta droop". (Both effects are less pronounced in good transistors.) With lower beta comes higher r_out.
Back to our output stage. Let's use the common class AB push-pull type, start at midpoint (0 V output) and go up:
1. At first we are seeing idle current flowing through both transistors, and virtually no current flows into the load. Small signal wise, both transistors are now driving the load in parallel.
2. As voltage rises, the bottom transistor turns off and only the top one drives the load.
3. As voltage rises further, we may or may not reach the kind of currents needed to exhibit beta droop. If we do, output impedance increases, and output voltage suffers. Lower-impedance loads mean more current, hence more severe beta droop.
Now let's look at phases 1. and 2. again and distinguish two interesting cases:
a) Very low idle current. Now beta at midpoint becomes very low, r_out shoots up and relative signal level at the load drops off like a rock. You're getting sort of a "notch" on the middle. At no idle current at all (pure Class B), this "notch" potentially extends up to plus or minus one V_be, i.e. up to about +/-0.6 V. Very nasty crossover distortion results.
b) Rather high idle current, enough to reach that beta "plateau". Now the output impedance at midpoint (where both transistors are operating) is only half as high as further up or down (where only one transistor operates), and you see a gentle "bump" in signal levels there. This effect is referred to as "gm doubling". If it extends to the entire output amplitude, we are looking at Class A operation (which is defined by neither transistor ever turning off).
In practice, you'll be trying to choose idle current such that both of these effects just about cancel out, which gives minimum distortion at high output levels (even if the midpoint region does remain somewhat uneven). Another school argues that lower levels are more common in practice, and prefers "fat" AB operation with a low-distortion "gm doubled" (Class A) zone extending as far as normal volumes will demand, an approach that also has its merits even if distortion at higher levels is substantially worse. (Pure Class A operation in a decent-sized loudspeaker amp tends to require substantial power supplies and cooling, aside from being heavy on the power bill.)
Note that yet again, the severity of these two effects worsens with lower load impedance.
Douglas Self has a nice discussion of output stage linearity in his power amplifier book, with plots and all for various types.
Question.... Is it possible to have an amp that has lower THD into 4R than 8R?
I've seen this in sims, is it possible in reality?
I've seen this in sims, is it possible in reality?
Not without doing something strange in the design.
Sims often give very optimistic results as they don't model beta droop and charge storage properly and make npn and pnp devices exact comlements, causing distortion cancellation
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