You don't. That's the switching threshold, where the NMOS and PMOS conduct equal current.
Yes. Then I read it right. The P-Channel source connects to Vcc (say 5V). The switching voltage of the pair is at ~1.5V, where it draws maximum current.
That means the TH voltage (e.g. Id > 100uA) of the N-Channel is a little higher, say 1.7V from Vss and the TH Voltage of the P-Channel is a little lower, referenced to Vss perhaps 1.3V.
But the P-Channel transistor must reference Vcc, so it's TH voltage would need to be 3.7V.
Presumably, while 3-4V TH are common in switching Fet's, they are uncommon in logic, so perhaps a zener (connected FET) or Vgs mutiplier is implemented in the source line to shift the threshold vs a near 1V threshold.
According to the document you linked to: "The threshold voltages Vt of the transistors are, in this case, about 1 V."
Well, that statement is at odds with the observed supply current vs input voltage.
Still, the typical overlap current at 3.3 V in and 5 V supply is not as bad as I thought, at least not for Schmitt trigger inputs of TI SN74AHCT chips, according to figure 6 of the same document. I guess they put a diode-connected PMOS in series with the PMOS side to reduce overlap current.
Well, they do something. And it works.
Incidentally, the document has also data on simultaneous switching, ground bounce and many other interesting topics, that were mentioned and queried here.
Thor