Groner's Low noise measurement amp from Linear Audio vol 3 - spare boards?

I have a question regarding the JFET matching. Vgs is measured with a voltmeter via TP303 and TP302. (Good technique to design this simple matching jig into the board.) But isn't it the matching of JFET transconductance that is important and similar values of Vgs might occur amongst JFETs with varying transconductance? Perhaps I have all this confused. My DMM is about as cheap as one can get, but I do own a Peak Atlas DCA Pro which can be used to measure JFET transconductance. Albeit much more fiddly than using the board's jig, I'm wondering if this would be better.

Also, one of the specs relates to balanced output. (I note the design abandoned balanced input.) How should one couple the output connector J102 correctly for balanced output versus single-ended output? I'm planning to use this, in the first instance at least, with a sound card (ESI Juli@ XTe) and ARTA. The sound card is setup for balanced input.

Apologies if these are basic questions. :eek:
 
Regarding JFET matching I'd note the following two points:
* Transconductance is a pretty dependable parameter; for a given drain current (and Vds and temperature), the transconductance amongst different specimen should be pretty close. Not as consistent as for BJTs, but still close (I don't have any data, but I'd expect worst-case tolerances below 10%).
* All JFETs are forced to operate at the same Vgs (as source and gate are shorted together). They will only operate at equal drain current, and thus very similar transconductance, if their "standalone" Vgs at the desired fractional drain current is matched.

Pin 3/4 of J102 go to pin 2/3 of the output XLR.

Samuel
 
Thanks.

All soldered. (Whoever invented cylindrical surface mount parts needs their head examined.) Hopefully I got the orientation of the op amps and diodes correct. Will power it up tomorrow. How/to what should bias be set?
 

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@ SGK: Damn, are you fast! I haven't even finished my order yet .....
How many JFETs did you order, and how was your yield during matching?

@ Samuel Groner: How would one verify the correct (basic) functionality of an ultra-fancy LNA like yours without ultra-fancy lab equipment? Measure the thermal noise of several resistors and do the math? Build a divider and feed it with a signal generator and hook it back up into a scope? Replace sig-gen and scope with a soundcard?

Best regards,

hallodeletue
 
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How would one verify the correct (basic) functionality of an ultra-fancy LNA like yours without ultra-fancy lab equipment? Measure the thermal noise of several resistors and do the math? Build a divider and feed it with a signal generator and hook it back up into a scope? Replace sig-gen and scope with a soundcard?

Gain and rough frequency response should be easy to measure with a basic function generator or sound card (perhaps with additional pad) and a scope or DMM with wideband RMS function. To verify the noise performance I'd measure output noise with shorted input and a 1 kOhm source resistor.

I meant trimming out the "residual DC offset" in the DC servo via R304. Trimmed to zero but where best to measure.

At the output--doesn't really matter where...

Samuel
 
Vgs at what current?
Normally we do the easy measurement by setting Vgs to zero volts and measure the current. If the jFET is cold and the Vds is as specfified in the datasheet we get Idss. If the Gate to Source voltage is measured with very low Id, we get Vp.
But a Vgs of 0.51v does not tell you much.
 
First, apologies but there should be a negative sign in front of those voltages i.e. -0.51-52V.

From post 22:

* All JFETs are forced to operate at the same Vgs (as source and gate are shorted together). They will only operate at equal drain current, and thus very similar transconductance, if their "standalone" Vgs at the desired fractional drain current is matched.

I think I would edit the above slightly: as their sources and gates are shorted together.

Have you read the article? The 'matching jig' on the pcb holds the gate at 0V and Vgs fluctuates with each transistor as a result of varying transconductance / Ids. If Vgs for each is identical/matched then Ids at that Vgs will be the same for each and they can be paralleled with confidence. Perhaps I'm missing something.

I still haven't bothered to get my head around why the 'matching jig' resistors R306 and R307 need to be their listed values in order to force "the desired fractional drain current."
 
The first part is the way we have learned from the forum as I would put it.

"I still haven't bothered to get my head around why the 'matching jig' resistors R306 and R307 need to be their listed values in order to force the desired fractional drain current."

For this I need to read the article which may enlighten part 1 as well. Hope the scattering of this forum would take an end as nothing about it can be personal. People do carry away from time to another thats life. Let them be and lets carry on and welcome them back when they feel ready.

There must be a bunch of thinkers that have a great deal to add to this subject!

Regards
 
First, apologies but there should be a negative sign in front of those voltages i.e. -0.51-52V.

From post 22:



I think I would edit the above slightly: as their sources and gates are shorted together.

Have you read the article? The 'matching jig' on the pcb holds the gate at 0V and Vgs fluctuates with each transistor as a result of varying transconductance / Ids. If Vgs for each is identical/matched then Ids at that Vgs will be the same for each and they can be paralleled with confidence. Perhaps I'm missing something.

I still haven't bothered to get my head around why the 'matching jig' resistors R306 and R307 need to be their listed values in order to force "the desired fractional drain current."
You have quoted a paragraph that states "as their sources and gates are shorted together."
That means Vgs = 0 (zero) volts

Later you refer to measuring Vgs at an Id.
That is in effect plotting one point in the Id vs Vgs graph.
A good method if you know the current.

I don't think I have seen the S.Groner paper. Is it only available as a "paid for" download?
 
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Here is what I get when I short the input to the pre-amp.

I'm just learning how to use ARTA. I have gone through the sound card calibration and setup process. My sound card is an ESI Juli@ XTe and I am using the balanced inputs (1/4" phone connectors). I entered 1000 as the pre-amp gain in ARTA.

I constructed a cable using Gotham Ministar Quad with a Neutrik NP3C-BAG phone connector on one end (stereo for use in balanced mode) and two clips on the other end. The pre-amp isn't yet in an enclosure and so I left the shield unterminated. The "tip" wires were connected to pin 3 of J102 the output of the regulator (third hole from left when looking into the connector) and the "ring" wires were connected to pin 4 of J102.

The pre-amp is powered by 9V batteries.

The output is hyper sensitive to the environment. Just pressing the foam can make a massive difference (usually settling the output lower).
 

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