Looks very fine, but maybe a mosfet cascade with the Q1 and 2 the rail voltage can be higher and so more headroom.

Nelson, you mentioned Q3 & Q4 are 25W devices. Can I take it that we are using something other than the IRF610 and it's compliment?

oooooh Greedy Lazy Boyz

Papa must do all hard work for ya .....

here it is - nomenclature by schmtc :

" This is familiar enough. Q1 and Q2 are JFETs which self-bias into resistors R3 and R4 at currents around 8 mA. R1 is chosen to avoid oscillatory interaction with whatever source impedance you might have, and R2 provides a DC reference to ground in the event that the source does not, and also establishes the nominal input impedance.

Q1 and Q2 are largely degenerated by R5, setting the amount of AC current which flows through them for a given input voltage. The voltage gain of this initial stage is approximately

the value of Drain load resistors R6 plus R7 divided by R5. In this case we have roughly unity gain – the Jfets are used as unity gain DC level shifters to Q3 and Q4.

Coming off the Drain of Q1 is the loading network of R6, C1 and P2, and there is a comparable network of R7, C2, and P1 attached to the Drain of Q2. R6 clearly sets the AC load for Q1, but the DC requirements to bias up Mosfet Q3 are higher than that, so P2 in parallel with C1 provides a higher resistance value below about 0.5 Hz, and gives the approximately 3 volt DC drop required to bias the Mosfets.

P1 and P2 are adjusted so as to set the DC bias of Q3 and Q4. You will want to set them at zero when you first fire up the circuit, and increase their resistance to achieve the correct bias voltages across R10 and R11 (about 1 volt) while also keeping the output DC offset voltage at a minimum. This circuit is capacitively coupled at the output, but low offset measured at the Drains of Q3 and Q4 will maximize your output voltage swing.

The voltage appearing at the Gate of Q3 is amplified by something less than the ratio of R13 divided by R10, and with the same happening at Q4(R11) and considering the transconductance of the Mosfets, comes out at about 15. Both of them added make a system voltage gain of about 30X, or 30 dB.

R10 and R11 help set the voltage gain, and they also help stabilize the bias of Q3 and Q4, else it would tend to drift upwards as the parts warm up. The bias current here is about 50 mA, and it will deliver peaks of approximately 100 mA. Q3 and Q4 require heat sinks.

Of course you can bias this circuit higher if you wish – 100 mA bias is perfectly OK as long as you properly heat sink Q3 and Q4, and if you are crazy (like me) you can experiment with higher bias, remembering that the parts are rated at 25 watts, and that it costs you voltage losses across R10 and R11. If you want to play with even higher bias, you can consider lowering the values of R10 and R11 and also R13, all in proportion.

The supply voltage is only critical with respect to the voltage rating of the input JFETs, which are nominally 25 volts. In actual testing, they break down around 40 volts. I wouldn't worry about running them as high as 30V. Hot-rodding this circuit would likely involve cascoding the input Jfets to allow higher voltages. "

lucky you ;

I still don't understand it

Hello everyone, this is my first note on the diya forum. I'm from Italy and I would like to recognize this forum as the best in the world concerning diy audio equipments. Sincerely. I'm really positive to build this front-end, but I would like to know which output stage would be worthful to couple with it. Thank you in advance for any suggestion.