Someone said why our forum have no any FPGA-based DAC. So It’s here now. I hope someone will interested in and discuss
This DAC will be compatible with Raspberry Pi and any I2S signal.
About DAC:
+ Auto detect sampling rate upto 768khz and bitdepth upto 32bit
+ Asynchronous I2S FIFO with 2 clocks for 2 sampling rate families (x44.1 and x48)
+ Upsampling or Resampling
+ FPGA-based Delta-sigma DAC with digital filter and noise shapping.
Board Detail:
+ Intel/Altera Cyclone IV FPGA
+ 2 clocks with precision power supply (ADM7150)
+ Power supply 5V or all individual voltage for Diyer upgrade (1.2V, 2.5V, 3.3V)
This DAC will be compatible with Raspberry Pi and any I2S signal.
About DAC:
+ Auto detect sampling rate upto 768khz and bitdepth upto 32bit
+ Asynchronous I2S FIFO with 2 clocks for 2 sampling rate families (x44.1 and x48)
+ Upsampling or Resampling
+ FPGA-based Delta-sigma DAC with digital filter and noise shapping.
Board Detail:
+ Intel/Altera Cyclone IV FPGA
+ 2 clocks with precision power supply (ADM7150)
+ Power supply 5V or all individual voltage for Diyer upgrade (1.2V, 2.5V, 3.3V)
Attachments
Hi tigerente,
Your project looks very promising. Can you tell us more? How does it sound?
I also want to do my next project a DS DAC, FPGA based, for Rpi.
The current one is R-2R DAC (last 5-bit MSB --> 31-bit thermometer), so only decimate filters for DSD(DoP). 24-bit ladder, Altera Cyclone IV, dual 90.xxxx/98.xxxx SiLabs osc.(so 768 max), DAC as master (so no FIFO need).
Your project looks very promising. Can you tell us more? How does it sound?
I also want to do my next project a DS DAC, FPGA based, for Rpi.
The current one is R-2R DAC (last 5-bit MSB --> 31-bit thermometer), so only decimate filters for DSD(DoP). 24-bit ladder, Altera Cyclone IV, dual 90.xxxx/98.xxxx SiLabs osc.(so 768 max), DAC as master (so no FIFO need).
Attachments
This DAC design have already done in a part of commerce product. It is just only re-designed for Raspberry Pi and for DIYer.
I think we are same hobby, I've also done a R2R DAC
Attachments
There were already several of those, but the more the merrier of course:
My no DAC project. FPGA and transistors.
https://www.diyaudio.com/forums/dig...simple-dsd-src-beaglebone-15.html#post6590662 (refers to a specific post of the "Simple DSD SRC for BeagleBone" thread, not to the whole thread)
Valve DAC from Linear Audio volume 13
74AHC02 and 74AHC08 DAC with 97 dB(A) dynamic range
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Does that mean you have to be careful with what you share because of company confidentiality or are you free (and intending) to make everything public?
😀 copyright by my 😉😉😉
This board design has already re-designed for Raspberry and DIY purpose
Also re-coded for raspberry.
So I can't share enough information for us to continue this project.
Preamplifier design is in attachment
Attachments
There are still differences between them. Tigerente’s DAC is more like a chord dave, which implements the DAC function purely on FPGA.
The low-priced AS318-b has better performance than CCHD-957, you can consider using it.
Chord is also my favorite brand, hope you can join with us this diy project to make a FPGA DAC with low cost
Wow, nice information, I will try it.
Raspberry's I2S signal is not good and unstable, My DAC need to add Asynchronous FIFO, upsampling and interpolation to make the signal more precisely and stable. So Oscillator is very important.
I will try AS318-b.🙂
If you are interested in AS318-b, you can contact me, I am one of the retailers in China. AS318-b is actually a clock made in China.
iancanada has designed a very complete set of processing methods for Raspberry's I2S signa. You can save a little effort to deal with this part of the work, and focus more on the FPGA-based delta sigma DAC itself. You can design a module that is more compatible with iancanada, which can also increase the barriers for others to join your project. In iancanada’s solution, DAC is only implemented using DAC chips.
GitHub - iancanada/DocumentDownload: Download documents of Ian's products
If your project may be able to enhance the DAC module of iancanada, and then get the attention of iancanada's fans.
I am very happy to join this project, but how do I join?
🙂 My DAC integrated I2S FIFO already, I want to provide a compact and low cost solution with high precision data
So the FPGA's I/O banks are used as the DAC?
Tigerente, do you do anything special to keep crosstalk between the digital processing and the I/O banks that are used as DACs under control? Just dedicate an I/O bank for the outputs (or two, one for left and one for right) and supply them from a nice low-impedance low-noise power supply, or is there more to it?
If your DAC isn't a master, An overflow finally occurs even if you have a FIFO. Three solutions are available. One is to be a master, the 2nd is ASRC, and the 3rd is clock recovery from LRCK because LRCK isn't jittery while BITCK is terribly wrong. I usually take the 3rd. 🙂
I'm not familiar with Altera but guess QFP usually doesn't have enough resource like xc6slx9. It's impressive to implement a two-channel DSM modulator, including an oversampling filter. How many multipliers does your FPGA have? How many order DSM did you design? Very interesting.🙂
Clocking Hell.
Err I mean each of those three FPGAs will have it's own master clock and you need a sync clock.. and the bit stream clock.
I thought the easiest way was to run a set of shift registers and then sync the switching as one. They would be cheaper than using an FPGA for the same role - that way you only need one. Which is pretty much what most of the FPGA R2R DACs do.
just use some I/O to be delta sigma output or discrete FF (like a CHORD 😀)
After that, the signal directly come to analog filter.
I think use FPGA, we can provide balance signal with dc offset
Input is I2S, how it can be master? can you talk more about it? 🙂
I think 2nd is the best. Re-clocking from any lower to high freq will cause terrible noise, jitter... clock will bad.
ha ha, Altera and Xillinx are always unclear about the way they count. They are different way - maybe the marketing purpose.
But deltasigma not use too many, 3, 5, 7 even 11 order spend not too many element. Filter will use almost resource - element and multiplier.
We have to combine parallel and series protocol to save resource.
Yes, that a good idea to save cost if you have a good I2S signal enough or DSD output.