First of all, I don't know if this is the correct forum to post on, if not appropriate, mods please move the thread.
I need to route a mostly digital board with lots of 100 ohm differential pairs that most likely will have to cross each other on different layers. Also there will be the need for a large 3.3V power supply plane.
This is the board stackup:
As using the first prepreg height of 0.0994mm yields impossible trace withs and spacings for a 100 ohm controlled impedance pair I came up with the idea to have no ground plane on layers 1 and 2 from the top and place the ground plane on layer 3 from the top and leave room for diff pairs on layers 1 and 2. Problem is then there is no shielding between them should they cross each other. where would I put the power plane then, layer 4? this would lead to diff pairs on the bottom two layers being routed over the power plane, probably not desireable?
What's the recommended way to go aboout this stackup?
Here's that the impedance calulator comes up with with minimum spacing of 0.127mm (manufacturer requirement) and a spacing to the ground plane of 0.55m:
I need to route a mostly digital board with lots of 100 ohm differential pairs that most likely will have to cross each other on different layers. Also there will be the need for a large 3.3V power supply plane.
This is the board stackup:
As using the first prepreg height of 0.0994mm yields impossible trace withs and spacings for a 100 ohm controlled impedance pair I came up with the idea to have no ground plane on layers 1 and 2 from the top and place the ground plane on layer 3 from the top and leave room for diff pairs on layers 1 and 2. Problem is then there is no shielding between them should they cross each other. where would I put the power plane then, layer 4? this would lead to diff pairs on the bottom two layers being routed over the power plane, probably not desireable?
What's the recommended way to go aboout this stackup?
Here's that the impedance calulator comes up with with minimum spacing of 0.127mm (manufacturer requirement) and a spacing to the ground plane of 0.55m:
So what’s you proposal stack up for this 6 layer design? It’s not clear to me what you decided. Signal/Signal/Ground/Power/?/?.
I common stack-up for 6-layer boards is: Signal/Ground/Signal/Power/Ground/Signal
I’d be really surprised if you cannot route differential pairs you need using the above stack-up.
I common stack-up for 6-layer boards is: Signal/Ground/Signal/Power/Ground/Signal
I’d be really surprised if you cannot route differential pairs you need using the above stack-up.
yes, indeed, but see below, it's the first time I consider a 6 layer board so I'm still confused.
I'd much more prefer this. I obviously made a mistake when using the impedance calculator, it was spitting out diff impedances in the 24 ohm range.
I did it again and it looks much better:
Thanks for your reply, sometimes I just need a little input after working and head scratching for hours.
It makes much more sense for me now and the stackup you proposed seems very intuitive now. Will try that in the following days. Having three signal layers available will GREATLY ease things for me as opposed to a 4 layer board. Also the availability of a complete power plane is much appreciated.
PS: for layer 3 (signal) sandwiched between two planes (power and ground), can I ignore the changed impedance as the power plane (layer 4 from top) is pretty far away (0.55mm) as opposed to the second layer (ground plane, 0.0994mm to the 3rd layer)? I yet have not found an impedance calculator for inner layers.
EDIT: planes got confused, corrected.
With grounds above and below it's called a stripline rather than a microstrip, if I'm not mistaken. Chances are that calculators assume equal distances and dielectrics on both sides.
Does anybody know of an "Asymmetric Edge Coupled Stripline Differential Impedance Calculator". Seem to find an "Edge Coupled Stripline Differential Impedance Calculator", but it assumes symmetric placement between the two planes above and below.
I don’t think these calculators are that accurate, but they give a target. If you can find a strip-line just use it and don’t worry about asymmetries.
Why do you need differential pairs for this project?
Why do you need differential pairs for this project?
1. thanks to 6 layers I am now pretty confident that I can place all diff pairs on top and bottom layers, directly above the ground planes. This will leave the rest of the signals which are rather non-critical like I2C, power good signals, etc. on layer 3 from the top, between power and ground plane.
2. I'm aware that these calculators are not 100% accurate, being in the range of 90-110 ohms will be sufficient I think, at least based on my experience with SWR deviations on antenna lines as a licenced ham operator.
We're building a modular 14 channel DAC project where the clock and I2S signal distribution is handled by sending LVPECL differential signals out from the "Motherboard" which will handle 14ch@192k/32bit by using a XMOS chip, local clock generation and as I said distribution to the mono channel DAC boards via ehternet cables.
The DAC boards will be housed in a modular case like this: https://www.bopla.de/gehaeusetechnik/interzoll
I will make everthing open souce once finished, if someone wants to take a peek:
- DAC Board, already finished: https://gitlab.com/t-5/dac-dr
- DAC Bus-Bar board for Interzoll housing with 24V SMPS and filtering on it, also pretty much finished: https://gitlab.com/t-5/dac-dr-busbar
- Motherboard Clock distribution. also finished: https://gitlab.com/t-5/DAC-DR-MB-ClockDistrib
- Motherboard main board, still very much in progress but schematics are finished: https://gitlab.com/t-5/dac-dr-mb
- Relay controller board for controlling amp output relays and power good handling, finished: https://gitlab.com/t-5/dac-dr-mb-relaycontroller
Correct, though it's pretty common to see 'stripline' used for microstrip. Always check the documentation for the calculator.
Tom
Since i got your valued attention, here are some more pcb design related questions:
- There are series termination resistors on single ended digital lines in the order of ~50ohms. this seems to be good practice. I assume these go on the receiving end, otherwise signal integrity would be harmed by forming a RC filter with the trace capacitance to the GP?
- what are your thoughts about a ground plane on top and bottom layers, are these necessary or even detrimental?
- what are your thoughts about via stitching, is it necessary/beneficial? If so, what's the recommended via distance? I've seen (and done) boards with excessive via stitching with a 2.5mm distance...
1. Series termination resister should go on transmitting end, not receiving end. The working principle of series termination is to turn the signal energy bounced back from the receiving end into heat, so that the receiver does not see an echo. Therefore, the transmitting device is de facto far end of the entire journey where a termination resistor should be situated. In other words, with series termination scheme, the signal energy travels a round trip. When the termination resistor, along with the equivalent signal source impedance, matches the transmission line characteristic impedance, the trace disappears, so does the trace capacitance (and the trace inductance, too).
2. You are talking about coplanar waveguide microstrip construction. It does provide more compact field confinement and allow for higher routing density than microstrip. PCB fab houses favor high copper coverage designs too. The routing density shown in the above layout does not need help from coplanar ground design. But a coplanar ground design will do no harm there either.
3. via stitching helps in coplanar waveguide designs. We usually use stitch pattern of 0.05" -- 0.150" pitch. Stripline construction usually does not require ground stitching, sometimes it's better no having vias around. We have had 25Gbps differential pairs that had no via stitching at all.
I really like Nattawa’s answer. I don’t have much to add apart from how to think about question 2.
When you have a signal travelling above a ground plane, the return current is directly underneath the signal trace. Imagine electric fields lines emanating from the trace and connecting to the ground plane. What is crucial is that the signal layer references a ground.
Adding an additional ground plane on top might be totally unnecessary if the fields are already well coupled to the ground plane.
Containing fields inside the PCB will help with radiated emissions, but unless you have very high speed/raising edges I doubt it will make a difference.
When you have a signal travelling above a ground plane, the return current is directly underneath the signal trace. Imagine electric fields lines emanating from the trace and connecting to the ground plane. What is crucial is that the signal layer references a ground.
Adding an additional ground plane on top might be totally unnecessary if the fields are already well coupled to the ground plane.
Containing fields inside the PCB will help with radiated emissions, but unless you have very high speed/raising edges I doubt it will make a difference.
This calculator is pretty good.
https://saturnpcb.com/saturn-pcb-toolkit/
You could also look up QUCS Studio. I think that it can synthesize lines for asymmetrical groundplane spacing.
https://saturnpcb.com/saturn-pcb-toolkit/
You could also look up QUCS Studio. I think that it can synthesize lines for asymmetrical groundplane spacing.
Thanks for this helpful explanation! Turns out I completely had misunderstodd what the resistor was for. Have moved all ersies termination resistors on the board to the transmitting side now and in the process cleaned up the traces considerably.
OK, then there will no ground plane on top and bottom and also no via stiching. Less work, yeah! 🙂
One more question: if I have a 3.3V CMOS signal at ~25MHz and a trace length of < 40mm - does a series termination resistor make sense at all? given the wavelength of the fundamental of > 10m - I would tend to say No.
It is not the frequency, but the edge rate tr/tf, that matters. A rule of thumb is that, if it takes more than 1/6*tr for the signal to cover the length of a wire, one should start to watch out for transmission line effect. Say, for a signal that has tr at 5nS travelling down a PCB trace at 50% speed of light (assuming the substrate dielectric constant at 4), the distance the signal propagates within 5/6 nS would be about 125mm. That would be the maximum trace length without having to involve signal integrity in the picture. Today there are modern CMOS devices that are capable of terrifying edge rates, well under 1nS being not uncommon. 40mm would then be a trivial trace length no more.
In practice, I'd put in a series resistor, usually 0603 or 0402 package and be done, regardless trace length and the edge rate. Even if the trace is short, the resistor can serve as a probing point. It does no harm.