Scored 4 pcs of 2SK79. I am thinking of a DIY pre-amp that can swing +/- 50v output in tribute to the XP-30. I am thinking of the DIY Sony VFET front-end.
By the way, the 2SK79 datasheet shows pins 1,2,3 as E-B-C. The gate of this SIT is pin 3. The datasheet is wrong.
Here are the musings. An n-channel SIT is a variant of an NPN transistor but it has a grid-shaped gate. When Vg > 0, you can see some normal NPN transistor behavior mixed with some SIT behavior. The curves become concave down like a normal BJT but with a very small Early Voltage. You see ~normal BJT curves but they are rotated counterclockwise ~45 degrees.
Enjoy the curves
By the way, the 2SK79 datasheet shows pins 1,2,3 as E-B-C. The gate of this SIT is pin 3. The datasheet is wrong.
Here are the musings. An n-channel SIT is a variant of an NPN transistor but it has a grid-shaped gate. When Vg > 0, you can see some normal NPN transistor behavior mixed with some SIT behavior. The curves become concave down like a normal BJT but with a very small Early Voltage. You see ~normal BJT curves but they are rotated counterclockwise ~45 degrees.
Enjoy the curves
Yes, pins are S D G when viewing the flat side.
I built a 2SK79 preamp with a DN2540 buffer front and back and it does swing a lot of voltage. It is the preamp/front end for all of my SIT follower amplifiers.
I built a 2SK79 preamp with a DN2540 buffer front and back and it does swing a lot of voltage. It is the preamp/front end for all of my SIT follower amplifiers.
This is from the Amplimos web site. 2SK79 is on the list of SITs. My 2SK79 traces just like all of the other SITs in my stash.
I did some LTSpice simulations and I figured the 2SK79 input impedance was about 50k Ohm, so the input buffer was added to allow the use of higher impedance volume control. Hopefully my simulations were correct. 🙂
Measured curves, datasheet and pinout here:
https://github.com/mbrennwa/curvetracedata/tree/main/2SK79
https://github.com/mbrennwa/curvetracedata/tree/main/2SK79
Gate current is 200nA at 6V. That is 30 megohms. I think you can safely omit the input buffer. My guess is that the 2SK79 has higher input impedance than the MOSFET.
I'm a diyer with no theoretical electronics education, so many of these calculations are unfamiliar to me. I see that the electrical characteristics that you quoted are for Ta=25 degrees C, and Vds=0A (typo? should be V?). What would be values be at a typical in-service temperature and Vds? I was curious so I looked at my LTSpice simulation. The gate current was in the neighbourhood but Vgs was much lower. Of course, the simulation may not be representative of the real life situation.
My method of figuring out the circuit input impedance was to simulate the CCS loaded common source 2SK79 voltage gain circuit (with no buffers) in LTSpice, measure the signal output voltage for a given input signal voltage, then add a resistor in series with the circuit input and determine the resistor value that gave an output voltage that was one half of the original measurement. This resistor value represented the circuit input impedance.
My method of figuring out the circuit input impedance was to simulate the CCS loaded common source 2SK79 voltage gain circuit (with no buffers) in LTSpice, measure the signal output voltage for a given input signal voltage, then add a resistor in series with the circuit input and determine the resistor value that gave an output voltage that was one half of the original measurement. This resistor value represented the circuit input impedance.
There are 2 impedances. DC and AC. DC impedance is due to gate leakage and the impedance is voltage dependent. The apparent impedance is V_gate/I_leak.
JFET and MOSFET AC impedance is dominated by input capacitance. A capacitor's impedance is defined as Z=1/(2*pi*f*c)
The input impedance of a MOSFET or JFET is dominated by its capacitance.
JFETs are used in the input for OP amps because they are easy to drive.
The input capacitance of the 2SK79 is 16pF per the datsheet.
The input impedance is frequency dependent. 16 pf is ~500 k ohms at 20kHz and ~500 megohms at 20Hz
JFET and MOSFET AC impedance is dominated by input capacitance. A capacitor's impedance is defined as Z=1/(2*pi*f*c)
The input impedance of a MOSFET or JFET is dominated by its capacitance.
JFETs are used in the input for OP amps because they are easy to drive.
The input capacitance of the 2SK79 is 16pF per the datsheet.
The input impedance is frequency dependent. 16 pf is ~500 k ohms at 20kHz and ~500 megohms at 20Hz
I pulled out the 2SK79 collection again. I traced up to 25mA and ran gate voltage all the way to zero volts.
It looks to me that if you were to cascode and bias this part at 10mA, you would want a minimum of 15v Vds.
I am thinking an F3-like architecture for a preamp.
It looks to me that if you were to cascode and bias this part at 10mA, you would want a minimum of 15v Vds.
I am thinking an F3-like architecture for a preamp.
Looking at the curves in post #10 I'd say you want to take the 2SK79 to slightly higher DS voltage, where it seems to be more linear.
At 15v Vds and 10mA, it looks very linear. Keep in mind I am looking at a constant Vds and not traditional single ended operation. It looks more linear at 30v Vds.
Datasheet suggest 4mA Id @50V Vds, seems reasonable, hot but not burning. In case you find you really need the 10mA, perhaps it would be better to consider an E88CC, 10mA @ 90-100V. 🙂
A high Yfs jfet (ie. JFE150) should work better in an F3 style preamp, it's the Yfs that really matters.
A high Yfs jfet (ie. JFE150) should work better in an F3 style preamp, it's the Yfs that really matters.
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Taken both graphs from #14 and #10. Inserted two values of Rd from supply of 20vdc and 40Vdc, both to Id^ of 20mA.
Serious differences in perspective and analyzing results. Observation with a keen eye seems not really reliable.
The transfer linearity might be important, but the 'interspacing' between the (linearized) curves is what it is all about (intrinsic local solid state feedback with these Vfets as in vacuum triodes).
And a high Yfs, as rightfully noted by indra1. Hiraga preferred those too.
Notice that on very low Vgs, the curves bends convex, and with higher Vgs they bend concave. So where's the optimum?
(It shifts! And on those sweet spots is where the load line should be!)
Serious differences in perspective and analyzing results. Observation with a keen eye seems not really reliable.
The transfer linearity might be important, but the 'interspacing' between the (linearized) curves is what it is all about (intrinsic local solid state feedback with these Vfets as in vacuum triodes).
And a high Yfs, as rightfully noted by indra1. Hiraga preferred those too.
Notice that on very low Vgs, the curves bends convex, and with higher Vgs they bend concave. So where's the optimum?
(It shifts! And on those sweet spots is where the load line should be!)
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You took it up to 1.8 Watt!!!??? That's way over the specified limit. I would not do that with unobtanium parts.
Nevertheless your curves just confirm my earlier curve measurements. These parts are more linear at higher voltage and current.
Nevertheless your curves just confirm my earlier curve measurements. These parts are more linear at higher voltage and current.