A CCDA does have tremendous advantages, that is, on the power supply, like Broskie asserts; and maybe even more, it might be beneficient on the earth connection.
Two sidelines:
Two sidelines:
- I simulated a EAR circuit board once to find out best place to earth it, it was elsewhere than actually on my board... 1 mA on 0,5 ohm is not audible but the scope picks it up as spikes of low value, say 0,5mV RMS;
- a square wave is waht many people never see in real life. Although I once had an unfiltered NOS DAC that had just that: you need perfect step response in the amp too]
My interconnect cable is a twisted pair, not shielded. It is made by Isoda Cables. There is no hum (preamp output resistance is rather low I think) My amp is a SIT amp @ 90k in because there is a capacitor in to a buffer.
Yes, of course. But it is a quick and proper way to judge an amplifier's overall behaviour and performance.
Best regards!
The challenge seems to 'what is a good design for an all ECC82 line preamp'. I figured I'd offer this:
If low THD is the goal, the best simulated result I've found so far is a mu-follower with a buffered output with NFB wrapped around it. One way to do that with a minimum of active devices is to configure the 12AU7 as a 'bootstrapped pair', with shunt NFB wrapped around it.
The upsides:
The downsides:
Anyhow, here's what I came up with. It simulates really well. THD is 0.0075% at 1Vrms out into a 47k ohm load. Frequency response is down only -0.05dB at 20Hz and 20kHz.
C4 was only necessary with high capacitance loads (as in long runs of not very good interconnect cables). Without C4 and with a 1000pF shunt load, there was a bump of unwanted gain of a few dB up around 1MHz. Even 1pF would roll that off well enough, but 2.2pF killed it dead.
One way to improve this circuit would be to use a MOSFET instead of V2 (the cathode follower). A MOSFET source follower will have much higher transconductance which will lower output impedance, which should be able to drive the NFB loop and the load device better before problems happen.
If anyone else has suggestions, I'm all ears...
If low THD is the goal, the best simulated result I've found so far is a mu-follower with a buffered output with NFB wrapped around it. One way to do that with a minimum of active devices is to configure the 12AU7 as a 'bootstrapped pair', with shunt NFB wrapped around it.
The upsides:
- Maximum gain from V1 (the input stage) because of the bootstrapped load resistance acting as a CCS.
- Maximizing gain allows more of that gain to be used for NFB, lowering both distortion and output impedance.
- Cathode follower V2 (output stage) has low output impedance and is run at higher current so that it can better drive both the load and the NFB loop.
The downsides:
- The 'anode follower' shunt NFB makes input impedance kind of low. I chose 100k for the NFB loop series resistor, which means the input impedance is going to be a bit lower than that. That high of a resistance may cause a bit of noise. However, this circuit is designed to be used for line level signals (100mV and higher), so I think the resistor would have to be really noisy to cause an audible problem. (I could be wrong about that, though.)
- The above means the volume control should be a fairly low value one, like 10k, 25k or 50k at most. That volume control is going to be a tough load for something like a tube phono preamp with high output impedance. I always have a cathode follower or source follower on the output of my tube phono preamp, so that should not be problem in my setup. But it could be in yours...
- Because V2 (the CF) has a lot to drive, this circuit is going to be somewhat sensitive to really tough loads. But is the typical power amp going to present that tough of a load? I don't think so — but I could be wrong.
- Infrasonic stability is tough to maintain in this topology. If you're willing to use large value film caps to couple the stages and feedback loop, then it will work. A low impedance power supply will be essential. If you have objections to using coupling caps any larger than 0.47uF, then this isn't going to work, or you're going to have to accept rolled off bass response in the output.
Anyhow, here's what I came up with. It simulates really well. THD is 0.0075% at 1Vrms out into a 47k ohm load. Frequency response is down only -0.05dB at 20Hz and 20kHz.
C4 was only necessary with high capacitance loads (as in long runs of not very good interconnect cables). Without C4 and with a 1000pF shunt load, there was a bump of unwanted gain of a few dB up around 1MHz. Even 1pF would roll that off well enough, but 2.2pF killed it dead.
One way to improve this circuit would be to use a MOSFET instead of V2 (the cathode follower). A MOSFET source follower will have much higher transconductance which will lower output impedance, which should be able to drive the NFB loop and the load device better before problems happen.
If anyone else has suggestions, I'm all ears...
Last edited:
Interesting bootstrap.
Another idea is to have a mosfet in the anode of the U2. This will be connected DC at 60% above the output DC and the gate has a small cap to the output: 500K+1Meg//100nF. The anode sees the same voltage all the time, very much improvin g things. This is a common application for some designers.
Another idea is to have a mosfet in the anode of the U2. This will be connected DC at 60% above the output DC and the gate has a small cap to the output: 500K+1Meg//100nF. The anode sees the same voltage all the time, very much improvin g things. This is a common application for some designers.
- The bootstrap on U1 could go that way too but that is never seen before by me . . .
I don't understand.
U2 is the cathode follower.
Put a MOSFET in the anode of the cathode follower, "connected DC at 60% above the output DC". Do you mean the DC voltage at the cathode of U2?
"the gate has a small cap to the output: 500K+1Meg//100nF." -- Small cap to which output? The CF cathode?
R5 sees no DC current across it, so it also drops no DC voltage, like an infinitely large resistance. It then appears extremely large to AC signal.
One could make U1 a full-on mu-follower using a MOSFET CCS as the anode load for U1. That would maximize the gain of U1 to its fullest.
Then couple that to a cathode (or source) follower to buffer the output of the mu-follower so that it does not directly try to drive the NFB loop,
One could also add a MOSFET CCS as the cathode load for U2, improving the performance of that stage as well.
Now we have a 12AU7 with at least two MOSFETs added. Yes, that would be better, but the above circuit has no MOSFETs in it, which I assumed was part of the design goal.
As regards M2, I meant the mosfet on the anode. I see no apparent difference in the distortion ..
Incidentally, the LTspice THD prediction for the circuit in #144 looks pretty good for a lousy 12AU7 with no solid-state helper devices...
Interesting for me too your bootstrapped load feedback circuit above...
By the way, I had considered it a while ago as an alternative pre-stage to drive the 6L6gc S.E. but then abandoned in favor of the classic srpp.
I read the pros and cons, you mentioned the anode follower. Because of some impedance problematics you say, wouldn't it be better to use it "as it is" as a buffer rather than as a circuit inserted for line preamp?
PS: finally, thanks for the suggestion for distortion measurements with real load, I didn't know it was also relevant to take into account the cabling capacitance.
I'm not sure i understood what you meant but...
The bootstrapped pair is basically a mu follower turned sideways... the cathode follower being perched on top of the common cathode stage in a mu follower. Because it has gain, it's not just a buffer.
By 'anode follower' I mean a common cathode voltage amp stage with plate to grid (shunt) negative feedback. Maybe I'm using the term wrong.
The bootstrapped pair is basically a mu follower turned sideways... the cathode follower being perched on top of the common cathode stage in a mu follower. Because it has gain, it's not just a buffer.
By 'anode follower' I mean a common cathode voltage amp stage with plate to grid (shunt) negative feedback. Maybe I'm using the term wrong.
It really sounds great.
The CCS anode load of #144 is good too, I will use it in another board. I have used that in a driver for a 300B, it is very clean.
The CCS anode load of #144 is good too, I will use it in another board. I have used that in a driver for a 300B, it is very clean.
I note your plot says 1V rms. However, I have a feeling signals in LTspice are peak values so 0dB on the FFT is 1V peak rather than rms.
Cheers
Ian
Thanks Ian. Good point.
However, I compensate for that by setting the input level so that the output is 1.414V peak (1.4134V peak in this case).
Now, why is it that in some plots 0dB = 1V peak, and in this plot it shows 1V rms as 0dB?
I have no idea...
I have a PCB for this circuit, but without the bootstrapping (the first stage is just a plate-loaded common cathode stage, DC coupled to the MOSFET source follower, with shunt feedback). I've stuffed it with parts for 12AT7 as the input stage. I still need to put together a 300V PSU and get it all in an enclosure...
However, I compensate for that by setting the input level so that the output is 1.414V peak (1.4134V peak in this case).
Now, why is it that in some plots 0dB = 1V peak, and in this plot it shows 1V rms as 0dB?
I have no idea...
I have a PCB for this circuit, but without the bootstrapping (the first stage is just a plate-loaded common cathode stage, DC coupled to the MOSFET source follower, with shunt feedback). I've stuffed it with parts for 12AT7 as the input stage. I still need to put together a 300V PSU and get it all in an enclosure...
Last edited:
I don't know what happened, but somehow I think I uploaded the wrong FFT. I ran the circuit sim again and got even better results. Now, this is a simulation, I know. Real life could turn out much worse. But this looks promising for a circuit with no silicon in it...
The input was set to 615mV peak to get an output of 1.4135V peak (approx 1V rms). That's 2.3X gain (7dB).
This is into a 10k ohm load.
H2 is fractionally higher into a 50k ohm load, but so is gain. H3 goes down to nothing.
R4 is the build out resistor for the cathode follower, to suppress oscillation when used driving a capacitive load.
C4 kills a small spike in response that happens around 200kHz if driving a 1nF parallel load on the output. Granted, that's a lot of load C. But it could happen.
C1 is a big, ugly cap right at the input, which is necessary to ensure infrasonic stability — exactly as Ian predicted. 2.2uF yields -0.01dB at 20Hz; 1uF yields -0.05dB at 20Hz. 0.47uF yields -0.15dB at 20Hz.
The input was set to 615mV peak to get an output of 1.4135V peak (approx 1V rms). That's 2.3X gain (7dB).
This is into a 10k ohm load.
H2 is fractionally higher into a 50k ohm load, but so is gain. H3 goes down to nothing.
R4 is the build out resistor for the cathode follower, to suppress oscillation when used driving a capacitive load.
C4 kills a small spike in response that happens around 200kHz if driving a 1nF parallel load on the output. Granted, that's a lot of load C. But it could happen.
C1 is a big, ugly cap right at the input, which is necessary to ensure infrasonic stability — exactly as Ian predicted. 2.2uF yields -0.01dB at 20Hz; 1uF yields -0.05dB at 20Hz. 0.47uF yields -0.15dB at 20Hz.
Couldn't R1 be moved to the left side of C1 to prevent charge buildup, and R8 be decreased to 680k?
Best regards!
Best regards!
Yes, R8 could—probably should—be decreased in value. 680k would work. Lowering it to 470k didn't hurt anything.
The opposite-facing 15V zeners at the output area (D2, D3) are a voltage clamp so that charging of C5 at power-up doesn't send a blast of DC volts downstream.
R1 could be removed altogether. U1 grid has a DC path to ground through R6 and R8 anyway.
Strangely, these changes reduced THD even more. It's now down to an unbelievable 0.0024%. I find that hard to believe. I think LTspice is predicting significant distortion cancellation between U1 and U2. Sure enough, swapping out the 12AU7 models for different ones resulted in double the THD (up to 0.0075%). But I couldn't get a reading any higher than that, so I'm pretty sure this will be a low THD circuit in real life.
Here's what it looks like now...
The opposite-facing 15V zeners at the output area (D2, D3) are a voltage clamp so that charging of C5 at power-up doesn't send a blast of DC volts downstream.
R1 could be removed altogether. U1 grid has a DC path to ground through R6 and R8 anyway.
Strangely, these changes reduced THD even more. It's now down to an unbelievable 0.0024%. I find that hard to believe. I think LTspice is predicting significant distortion cancellation between U1 and U2. Sure enough, swapping out the 12AU7 models for different ones resulted in double the THD (up to 0.0075%). But I couldn't get a reading any higher than that, so I'm pretty sure this will be a low THD circuit in real life.
Here's what it looks like now...
Me too, I tried to run the circuit (as I said already got one as pre-stage for 6l6gt SE) modified according to above but i didn't find the amazing THD you got. Maybe it depends on the tube modeling in the simulation? Or other factors? What it came out is in the order of ten times higher ...
Just as a curiosity I tried to simulate the SLCF circuit (which I did not know before) and it actually has a very low distortion, 0.004%. Although this with silicon components, it looks pretty and possibly could be combined with a suitable previous stage.
Having never listened to it, I cannot judge its goodness anyway... some reading on an Italian forum says that it is very transparent.
I post the .asc file if someone may be interested.
Just as a curiosity I tried to simulate the SLCF circuit (which I did not know before) and it actually has a very low distortion, 0.004%. Although this with silicon components, it looks pretty and possibly could be combined with a suitable previous stage.
Having never listened to it, I cannot judge its goodness anyway... some reading on an Italian forum says that it is very transparent.
I post the .asc file if someone may be interested.
One reason why the SLCF will yield really low THD is that it is a buffer with 100% NFB -- it has no gain at all. It is a buffer, which means it offers a very high impedance at its input and a very low impedance at its output.
Another reason why the SLCF yields such low THD is that it uses lots of transistors to get the job done. Why not go all silicon?
Here is the .asc for the Boostrapped Pair 12AU7 with Shunt NFB circuit. It has 2.3X gain, but you can increase the value of R6 to get more gain (but with higher THD of course).
This version uses the older Ayumi Nakabayashi model for the 12AU7. I get 0.009% THD at 1V rms output (1kHz sine wave).
How are you measuring THD in LTspice? The way I do it is:
You should see the log file displayed. Scroll down to where it shows Total Harmonic Distortion as a percentage.
Another reason why the SLCF yields such low THD is that it uses lots of transistors to get the job done. Why not go all silicon?
Here is the .asc for the Boostrapped Pair 12AU7 with Shunt NFB circuit. It has 2.3X gain, but you can increase the value of R6 to get more gain (but with higher THD of course).
This version uses the older Ayumi Nakabayashi model for the 12AU7. I get 0.009% THD at 1V rms output (1kHz sine wave).
How are you measuring THD in LTspice? The way I do it is:
- Make sure the voltage source input is a 1kHz sine wave.
- Adjust the level of the input voltage source so that the output is a reference voltage (for preamps I'll use 1Vrms = 1.414V peak).
- Run the following:
Code:
.options plotwinsize=0
.tran 0 100m 60m 1u
.four 1k 20 v(out)
.OPTIONS numdgt=8
.option noopiter- Click the output node to see the output waveform in the .raw window.
- Select the .raw window.
- Go to View > SPICE Error Log
You should see the log file displayed. Scroll down to where it shows Total Harmonic Distortion as a percentage.
Last edited: