The ground pin length of that IC might be too long...
Try this as well; I think this will work better - lower ground impedance path at a much broader frequency spectrum... You'll also be able to provide a large contact (solder) area for the capacitor, which is very important. The un-decoupled Vcc pin length will be only slightly longer - it is more important to have a low impedance ground return path and large contact area, for the capacitor to work as it should.
The difference between what you suggested and what I am suggesting should be, actually, easily noticeable. It was for me... during the days I played with DIY DACs. Let us know the results... if you are willing to experiment, that is.
Try this as well; I think this will work better - lower ground impedance path at a much broader frequency spectrum... You'll also be able to provide a large contact (solder) area for the capacitor, which is very important. The un-decoupled Vcc pin length will be only slightly longer - it is more important to have a low impedance ground return path and large contact area, for the capacitor to work as it should.
The difference between what you suggested and what I am suggesting should be, actually, easily noticeable. It was for me... during the days I played with DIY DACs. Let us know the results... if you are willing to experiment, that is.
A quick reminder to all following this thread and based on the posts above: I am fine with anyone building their personal DAC-Boards. Nevertheless, it is not a dddac Design, so should not be called like that to avoid any misunderstanding. It also should not be sold. Not even to a friend a few leftover pieces. That is the "price" everyone has to pay, for me publishing in detail, all my designs with circuit diagrams, test reports etc.
I also like to remind Juluiobozek, that it is probably not OK to copy Tent-Labs (shunt regulator) designs, not even for personal use, as far as I am informed. Unless you have OK from Guido tent for that?
Anyway, aside from the official remarks, I am glad to see there is still a lot of experimenting going on and I would be interested if your C-on-IC-pin is really making a significant audible difference.
I do like to avoid an ongoing discussion on the pros and cons of decoupling in general in this thread. For that you should start a separate thread, as that topic could be endless ;-)
I also like to remind Juluiobozek, that it is probably not OK to copy Tent-Labs (shunt regulator) designs, not even for personal use, as far as I am informed. Unless you have OK from Guido tent for that?
Anyway, aside from the official remarks, I am glad to see there is still a lot of experimenting going on and I would be interested if your C-on-IC-pin is really making a significant audible difference.
I do like to avoid an ongoing discussion on the pros and cons of decoupling in general in this thread. For that you should start a separate thread, as that topic could be endless ;-)
Hi doede,
I am planning my DDDAC build for quite some time now.
Your above quote especially took my interest: I want to build full dual mono, AND by doing that I want to double the DAC decks per deck. So installing one deck means I already have two, for one channel offcourse.
However, I don't understand the quote by "rewiring the LR signal", as per schematics the LR signal is the only one that is shared for both Left and Right side DACs. I took the I2S wikipedia for details on understanding the digital signal (have some skill into understanding, not into I2S).
LR
Apparently the LR to DACboard can just be constant-low (to GND) for Left, and constant-high (to 5V) for Right, without R inbetween.
DATA
What also needs to be rewired in my opinion is the DATA(-39.5) and DATA(-7.5) (as these are the left and right alterations, different data), and
BCK
MAYBE the BCK-L and BCK-R signals. It depends what IC4 does with the BCKin signal, I suppose nothing but parallelling to BCK-L and BCK-R, in that case BCK can be left as is. EDIT#1: it can be left as-is, both -L and -R BCK signals get the same IN signal.
As for Rload, with just one deck installed on a mainboard, I just follow schematic recommendation as-per-normal, when bridging posL and posR together, and negL to negR, the Rload gets halved.
Concerning the INPUT signals (planning on working with RPi I2S + retaining the SPDif option):
- Can I just wire the I2S signal from mainboardL to mainboardR? It enters straight into IC4 with no R's or whatsoever.
- Can I just wire the SPDIF input to both boards? SPDIf is then seeing a 75/2 ohm input resistance, or do I need to double the R's to 150ohm?
- I would use a 2-pole switch for I2S-SPDIF selection.
I am in doubt to forget about SPDIF implementation, and use an iancanada ReceiverPi beneath the RPI, then these inputs could get to the DDDAC in 'cleaned' I2S form.
Could you please point me in the good direction on this? I may already be in that direction, who knows ;-)
Attached is a picture of the circuit, with RED modifications for LEFT channel, BLACK (pen) modifications for RIGHT channel.
Do you happen to have built a DDDAC in this alteration?
Thanks a lot!
Attachments
HI DCTRL,
Just wired the mainboard as indicated, that is enough, no need to tamper with BCK or anything else. Using 2x 150 Ohm is a clever idea for spdif and yes, just route through the power and I2S inputs signals.
in Summary to your question:
LR
Apparently the LR to DACboard can just be constant-low (to GND) for Left, and constant-high (to 5V) for Right, without R inbetween.
*** NO ! that would not work - use the scheme as indicated and leave LR untouched!
DATA
What also needs to be rewired in my opinion is the DATA(-39.5) and DATA(-7.5) (as these are the left and right alterations, different data), and
**** yes, see schematic
BCK
MAYBE the BCK-L and BCK-R signals. It depends what IC4 does with the BCKin signal, I suppose nothing but parallelling to BCK-L and BCK-R, in that case BCK can be left as is. EDIT#1: it can be left as-is, both -L and -R BCK signals get the same IN signal.
**** the BCK R and L are only buffered versions of each other, no need to change anything here
As for Rload, with just one deck installed on a mainboard, I just follow schematic recommendation as-per-normal, when bridging posL and posR together, and negL to negR, the Rload gets halved.
******* even that is not necessary, just leave the original Load resistors and wire R and L output together (it is a current output, so that will work fine)
Concerning the INPUT signals (planning on working with RPi I2S + retaining the SPDif option):
Just wired the mainboard as indicated, that is enough, no need to tamper with BCK or anything else. Using 2x 150 Ohm is a clever idea for spdif and yes, just route through the power and I2S inputs signals.
in Summary to your question:
LR
Apparently the LR to DACboard can just be constant-low (to GND) for Left, and constant-high (to 5V) for Right, without R inbetween.
*** NO ! that would not work - use the scheme as indicated and leave LR untouched!
DATA
What also needs to be rewired in my opinion is the DATA(-39.5) and DATA(-7.5) (as these are the left and right alterations, different data), and
**** yes, see schematic
BCK
MAYBE the BCK-L and BCK-R signals. It depends what IC4 does with the BCKin signal, I suppose nothing but parallelling to BCK-L and BCK-R, in that case BCK can be left as is. EDIT#1: it can be left as-is, both -L and -R BCK signals get the same IN signal.
**** the BCK R and L are only buffered versions of each other, no need to change anything here
As for Rload, with just one deck installed on a mainboard, I just follow schematic recommendation as-per-normal, when bridging posL and posR together, and negL to negR, the Rload gets halved.
******* even that is not necessary, just leave the original Load resistors and wire R and L output together (it is a current output, so that will work fine)
Concerning the INPUT signals (planning on working with RPi I2S + retaining the SPDif option):
- Can I just wire the I2S signal from mainboardL to mainboardR? It enters straight into IC4 with no R's or whatsoever.
- Can I just wire the SPDIF input to both boards? SPDIf is then seeing a 75/2 ohm input resistance, or do I need to double the R's to 150ohm?
- I would use a 2-pole switch for I2S-SPDIF selection.
I'm interested in multiple inputs but want to keep I2S leads short so a switcher or multiple input board in lieu of the WAVE IO would be nice. I want to retain a high quality signal at the same time so a board with SPDIF and I2S pass thru would be a good option as well.
Any future upgrades coming or someone making a board to switch digital inputs?
We were reorganizing our flat and I had my DDDAC stored upside down for a while after hooking it back up again last night. There was only a bit of noise and after looking around a bit saw, that the ground connector had slipped of from the I2S inputs. I connected it without switching the DAC off and instantly had music but only on the left channel. Could it be that the boards got damaged running without proper GND connection to the input signal?
I think the situation Bfpca described was not happening, as the main board has the Tent clock installed and the boards where still connected to the main board?
It is a 5 deck DDDAC, shunt version decks, current main board, fed from a Raspberry Pi with ReclockPi and FiFoPi into the I2S input.
I appreciate any help troubleshooting this. I checked all other connections and power supplies. That all checks out.
Hello Doede,
Congratulations on your succesful project. After looking through the project i quickly realised what you saw in it and the potential i had to see it for myself.
1. There is an output capactor to protect from the DC voltage that develops as a result of the dac current being offset by -6.2mA, with each new DAC deck then driving this lower and lower, and the resulting output DC higher and higher. In my testing already at a few dacs you get to 1.3v and higher, but for pcm1794 i read limit is something like 1.25v.
And indeed in my experiments when you go over this there is very steeply rising distortion spray of high harmonics, probably as the output diodes try to clamp it down or something like this..
Output capacitor only protect the device following the dac from the DC, but the dac itself still "sees" it, have you tried injecting current before I/V to offset the DAC's -6.2mA, like how they do it with TDA1541 for example (if you know what i mean), or some other method?
2. I read through pages of the thread and your site, but i didn't see anyone commenting this..During testing did you ever have issue with individual DAC's latching correctly?
Every time i turn on the dac a random number of chips will latch and others not, anywhere between 0 of them and all of them. If you quickly "tap" the BCK or LRCK line to ground with something like tweezers, the dice rerolls and you get random number of them re-latch, after like 50 attempts you can get the permutation where all them are working but this is obviously not ideal procedure every time you turn it on. I have 100ohms resistors on each line (LR,DATA,BCK) before each dac on each stack, but elsewhere on your site i see data should actually be 1k to compensate for the extra 1/2 clock cycle of HC164.
What i wrote is based on what i see from version 4.4 from 2016 on your website dddac.com, except for the power supplies which i used my own, mostly doing the 3.3v with a bunch of lp5907 (each dac has its own) fed by Jung superreg. Each DAC sits on its own 8 layer pcb
(I have no commercial interest, will not sell to anyone, did not use Tent's contribution, i agree with your comment above that you wrote to other person, i am just pursuing hifi like you) Also i am using PCM1798 after finding they are identical in every way except half the current, and slightly different filter which we are not even using, and 2.5$ a piece vs 25$, good enough for prototype.
Congratulations on your succesful project. After looking through the project i quickly realised what you saw in it and the potential i had to see it for myself.
1. There is an output capactor to protect from the DC voltage that develops as a result of the dac current being offset by -6.2mA, with each new DAC deck then driving this lower and lower, and the resulting output DC higher and higher. In my testing already at a few dacs you get to 1.3v and higher, but for pcm1794 i read limit is something like 1.25v.
And indeed in my experiments when you go over this there is very steeply rising distortion spray of high harmonics, probably as the output diodes try to clamp it down or something like this..
Output capacitor only protect the device following the dac from the DC, but the dac itself still "sees" it, have you tried injecting current before I/V to offset the DAC's -6.2mA, like how they do it with TDA1541 for example (if you know what i mean), or some other method?
2. I read through pages of the thread and your site, but i didn't see anyone commenting this..During testing did you ever have issue with individual DAC's latching correctly?
Every time i turn on the dac a random number of chips will latch and others not, anywhere between 0 of them and all of them. If you quickly "tap" the BCK or LRCK line to ground with something like tweezers, the dice rerolls and you get random number of them re-latch, after like 50 attempts you can get the permutation where all them are working but this is obviously not ideal procedure every time you turn it on. I have 100ohms resistors on each line (LR,DATA,BCK) before each dac on each stack, but elsewhere on your site i see data should actually be 1k to compensate for the extra 1/2 clock cycle of HC164.
What i wrote is based on what i see from version 4.4 from 2016 on your website dddac.com, except for the power supplies which i used my own, mostly doing the 3.3v with a bunch of lp5907 (each dac has its own) fed by Jung superreg. Each DAC sits on its own 8 layer pcb
(I have no commercial interest, will not sell to anyone, did not use Tent's contribution, i agree with your comment above that you wrote to other person, i am just pursuing hifi like you) Also i am using PCM1798 after finding they are identical in every way except half the current, and slightly different filter which we are not even using, and 2.5$ a piece vs 25$, good enough for prototype.