I was recently looking into building a simple Wordclock distribution system because for the first time I needed to sent Wordclock beyond the rack where my digital audio gear resides. Up to now I've been using traditional BNC T-connectors, wiring and terminator to send my primary AD/DA's clock to other converters.
I found an older now deprecated chip, the EL2099CT which is basically a high-frequency high-current opamp (EL2099 datasheet) with a 50 MHz bandwidth and a 1000 v/us slew rate, though spec sheet min is 500 v/us. The circuit I'm discussing here is on that spec sheet on page 11.
Power-wise, it can provide almost 0.5 amp to easily drive 6 - 75 ohm lines and makes for a really simple build. That slew rate, even at 500 v/us, pretty well guarantees decent performance to 500 kHz (1000 v/us) or even 1 MHz (500 v/us).
However, today's best clocks are rated in picoseconds and even femtoseconds, and I'm wondering how well a circuit like this can be counted on not to aggravate or induce jitter. Assuming good power supply filtering and stability, and proper EMI/RFI shielding, can this circuit provide clean Wordclock distribution at common audio sample rates? Thanks for any insights.
I found an older now deprecated chip, the EL2099CT which is basically a high-frequency high-current opamp (EL2099 datasheet) with a 50 MHz bandwidth and a 1000 v/us slew rate, though spec sheet min is 500 v/us. The circuit I'm discussing here is on that spec sheet on page 11.
Power-wise, it can provide almost 0.5 amp to easily drive 6 - 75 ohm lines and makes for a really simple build. That slew rate, even at 500 v/us, pretty well guarantees decent performance to 500 kHz (1000 v/us) or even 1 MHz (500 v/us).
However, today's best clocks are rated in picoseconds and even femtoseconds, and I'm wondering how well a circuit like this can be counted on not to aggravate or induce jitter. Assuming good power supply filtering and stability, and proper EMI/RFI shielding, can this circuit provide clean Wordclock distribution at common audio sample rates? Thanks for any insights.
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Thanks. There's some meat in those datasheets, but it's hard to compare digital specs to a totally linear circuit without the tools to test the linear circuit. This might be a lost cause...
If your clock output is a square wave then you need to determine the rise time as this will allow you to calculate the knee frequency and thus determine the required bandwidth if you are going to use an op-amp or similar.... A 1nS rise time give a knee frequency of 500MHz a bit wider than the device you have chosen... Using such a device may cause problems such as ISI (inter symbol interference), it would certainly round of your square wave.
If you want to drive cables, yes, single-end logic-swing drivers are probably asking for trouble.
Since this task is what LVDS was designed for, why not have a look at some modern differential parts?
For instance, the TI CDCLVD1204 is a twin-output clock driver, intended for low jitter & phase-noise (data sheet includes some measurements, but as usual, not as close to the "carrier" as we would like).
http://www.ti.com/lit/ds/symlink/cdclvd1204.pdf
This can accept LVCMOS clock signals in, and put out 2 LVDS clocks, optimised for driving 50 ohm transmission lines.
Plenty of other LVDS parts to compare, also.
As usual, the power supply design must be right up to snuff to avoid adding jitter. Allow for the performance of the RX end, too.
You'll need to design an impedance-matched board, and mount the leadless ICs with a hot-plate - but maybe all that would be fun.
The other neat thing about the TI chip:
It has a SELECT input, that allows you to choose the output clock from one of two sources - so you can have the 44.1k and 48k related oscillators, selectable without another layer of logic inputs & outputs.
It has a SELECT input, that allows you to choose the output clock from one of two sources - so you can have the 44.1k and 48k related oscillators, selectable without another layer of logic inputs & outputs.
Regarding LVDS, that's the way it should have been implemented, but in "pro-audo", Wordclock is still being inter-connected and transferred via single-ended 75 ohm BNC cables, with voltages ranging from +2 to 5 volts. I do see that I could run the chip as single-ended...
But I've come to the conclusion that any WC distribution is best done rght after a dedicated master clock to avoid any propagation delay issues, as opposed to using an AD/DA as the master clock. So I've decided to shelve this project for now.
Thanks for all the info and clarifications. Appreciated!
But I've come to the conclusion that any WC distribution is best done rght after a dedicated master clock to avoid any propagation delay issues, as opposed to using an AD/DA as the master clock. So I've decided to shelve this project for now.
Thanks for all the info and clarifications. Appreciated!
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