Hi,
in my DIY DAC, in the conclusion phase now - close to be boxed -, I did a lot of MODs in the last months, mainly concentrated on the analogue stage, PLL and DAC chips tuning.
I have been using CS8412 since the beginning without any adjustment in the PLL filter, as I read everywhere that the Windmonkysect filter (220nF+470R//3300pF) sounded the best.
As I saw many projects still using the standard 1K//47nF datasheet configuration, last week I started to change both the CAP and the resistor in the PLL filter on pin 20.
I used also the suggested rule that for any 'n' increase of C, should follow a 'SQRT
' decrease of R.
I saw discussions that pushing the highest possible value of C (at the expense of a longer PLL locking time), is even better for jitter reduction as it lowers the PLL low pass frequency. Someone have used C in the order of microfarads and even electrolytic too!
So I tested by ear different C values, from 1nF (which didn't work) to 4.7 uF.
Well, what I found the best sounding was against any empirical rule: a simple 6.8nF cap (but in Teflon) plus a resistor of 120 ohm from pin 20 to analog ground, and no more cap from pin 19 to pin 20.
In theory with a 6.8nF cap I should have increased R to 2630 ohm. But with high value resistors the sound was not the best.
I also tested no R (R=0), just the Cap, which was not good.
With 6.8nF + 120R combination, vocals, details and soundstage were the best (open, clear and mid forward) at the expenses of a slight lower dynamic in the bass: now energy in the low end is even more balanced.
As I was curious of this amazing solution, I run the J-test jitter, and I measured THD% at 0dB, -60db and -80dB. Jitter and -60dB distortion improved few decibels too! Jitter spectrum is now below the -115 dB. Frequency response is exactly the same, so the feeling of less dynamic in bass is probably due to a more mid-forward soundstage feeling.
I have to say that I'm also using a switchable cascade PLL external board containing a low jitter VCXO following the CS8412 and in sync with MCK, plus a fast comparator to recover the SPDIF signal before the CS8412: the sound improved a lot but mainly by using the PLL extra board.
My conclusion can be only that the PLL VCXO extra board is working better with a faster CS8412 PLL circuit, which now works with a much higher bandwidth.
Increasing the CS8412 loop filter bandwidth, should have decreased (I would say even nullified) the amount of jitter attenuation of the CS8412 on the reference source clock (that is the digital player plus the fast comparator which recovers the SPDIF input signal), and have increased the relative contribution of the cascade extra VCXO PLL which follows the CS8412.
The external PLL board is actually very slow and has a very low loop filter bandwidth (even reduced by :16 divisors in the feedback) which increases the amount of jitter attenuation on the reference clock (CS8412) transferring less jitter from the input to the output. This because I'm using now a very low noise VCXO.
In simple words, I think that with such low values in the PLL filter on pin 20, the CS8412 just locks the frequency and does nothing to recover jitter, which is better executed now by the comparator at the input and the PLL at the output. Are these the reasons?
Final suggestion could be: if you use a low bandwidth, low noise VCXO PLL extra board (and even an input comparator to recover Spdif signal) it is better to have the fastest possible PLL in the CS8412. The impact to combine two cascade PLL devices, both with very low bandwidth, could not form the optimum combination to clean jitter, or, even, have the detrimental effect of actually increasing the output clock jitter.
Do you agree?
in my DIY DAC, in the conclusion phase now - close to be boxed -, I did a lot of MODs in the last months, mainly concentrated on the analogue stage, PLL and DAC chips tuning.
I have been using CS8412 since the beginning without any adjustment in the PLL filter, as I read everywhere that the Windmonkysect filter (220nF+470R//3300pF) sounded the best.
As I saw many projects still using the standard 1K//47nF datasheet configuration, last week I started to change both the CAP and the resistor in the PLL filter on pin 20.
I used also the suggested rule that for any 'n' increase of C, should follow a 'SQRT
' decrease of R. I saw discussions that pushing the highest possible value of C (at the expense of a longer PLL locking time), is even better for jitter reduction as it lowers the PLL low pass frequency. Someone have used C in the order of microfarads and even electrolytic too!
So I tested by ear different C values, from 1nF (which didn't work) to 4.7 uF.
Well, what I found the best sounding was against any empirical rule: a simple 6.8nF cap (but in Teflon) plus a resistor of 120 ohm from pin 20 to analog ground, and no more cap from pin 19 to pin 20.
In theory with a 6.8nF cap I should have increased R to 2630 ohm. But with high value resistors the sound was not the best.
I also tested no R (R=0), just the Cap, which was not good.
With 6.8nF + 120R combination, vocals, details and soundstage were the best (open, clear and mid forward) at the expenses of a slight lower dynamic in the bass: now energy in the low end is even more balanced.
As I was curious of this amazing solution, I run the J-test jitter, and I measured THD% at 0dB, -60db and -80dB. Jitter and -60dB distortion improved few decibels too! Jitter spectrum is now below the -115 dB. Frequency response is exactly the same, so the feeling of less dynamic in bass is probably due to a more mid-forward soundstage feeling.
I have to say that I'm also using a switchable cascade PLL external board containing a low jitter VCXO following the CS8412 and in sync with MCK, plus a fast comparator to recover the SPDIF signal before the CS8412: the sound improved a lot but mainly by using the PLL extra board.
My conclusion can be only that the PLL VCXO extra board is working better with a faster CS8412 PLL circuit, which now works with a much higher bandwidth.
Increasing the CS8412 loop filter bandwidth, should have decreased (I would say even nullified) the amount of jitter attenuation of the CS8412 on the reference source clock (that is the digital player plus the fast comparator which recovers the SPDIF input signal), and have increased the relative contribution of the cascade extra VCXO PLL which follows the CS8412.
The external PLL board is actually very slow and has a very low loop filter bandwidth (even reduced by :16 divisors in the feedback) which increases the amount of jitter attenuation on the reference clock (CS8412) transferring less jitter from the input to the output. This because I'm using now a very low noise VCXO.
In simple words, I think that with such low values in the PLL filter on pin 20, the CS8412 just locks the frequency and does nothing to recover jitter, which is better executed now by the comparator at the input and the PLL at the output. Are these the reasons?
Final suggestion could be: if you use a low bandwidth, low noise VCXO PLL extra board (and even an input comparator to recover Spdif signal) it is better to have the fastest possible PLL in the CS8412. The impact to combine two cascade PLL devices, both with very low bandwidth, could not form the optimum combination to clean jitter, or, even, have the detrimental effect of actually increasing the output clock jitter.
Do you agree?
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Thanks for the positive comment.
Outdated does not necessarily mean it sounds worse.
By the way, there are 485,000 posts on "tubes and valves" in this DIYAUDIO forum.
Old technology has tons of documentation, schemes and worldwide experience on the Internet, which provide a stable basis for work theory and a great flexibility in modifications.
Like in this case: the PLL scheme I used is taken from M.Heijligers Tentlabs DAC, it works very well (Guido Tent said: "an improvement over any PLL based receiver chip") and it's really good after ten years. I modified it slightly to run with PCM56 and I adopted high performance ADI newest components.
For many years, CS8412 has been well regarded in the audio word for its sound quality and DIY flexibility. However, the synchronization of the oscillator on the chip is based on a capacitor and not on a crystal. As a result, it generates a significant jitter of its own.
So, I made CS8412 run "in an unusual way" with the widest possible bandwidth (with a cutoff frequency of almost 200 KHz, outside the audio band, which is always good): I never saw this! In this way, the receiver should act only for frequency capture, since it rejects jitter only above that high frequency.
The much lower bandwidth of the PLL (based on a VCXO) is used on the other side for "dejittering", which cleans the clock output of the CS8412. Also its bandwidth is outside the audio band, but in this case on the right side!
Measurements and listening sections have shown small improvements.
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