I have had a go at the LT circuit on Ki Cad and it is my first go with the software. My biggest concern with the schematic which I guess I should have asked earlier is if the paralleling of the R and C that create the slopes and boost have been done correctly.? I wasn't sure if that link between the parallel sections was required. I have parallelled up on R1 thru 3, and C1 thru 3, to give a chance of finding a close match for the calculated values.
I'm sure there are trace routings that could be optimised but as a first attempt I feel quite happy. I tried to amend the traces from 0.2mm to 1mm but the nets all swapped about from for some reason,
Please let me know if you see any glaring issues!
Thanks
I'm sure there are trace routings that could be optimised but as a first attempt I feel quite happy. I tried to amend the traces from 0.2mm to 1mm but the nets all swapped about from for some reason,
Please let me know if you see any glaring issues!
Thanks
Exactly. Then you will also discover traces between opamp pins is not advisable.
Also why waste one half of the opamp? You could use it as input buffer ...
Power and ground traces should be wide for low inductance. Do you have ground-pour to provide low-inductance path for the decoupling cap returns? Why aren't the resistors 0.4" pitch as is conventional? You are spreading out your circuit and providing more stray capacitance between signals with those wide resistor pitches, tighter layout is desirable for both lower stray capacitance, inductance and lower noise pickup potential.
The second opamp can be used as an input buffer so the filter actually works the same independent of source-impedance.
The second opamp can be used as an input buffer so the filter actually works the same independent of source-impedance.
If you run oblong IC pads 50x100 mils, you can run 2 tracks with 10/10 size and spacing
between pins with a DIP package.
I agree the traces are somewhat small. Have you considered a 4 layer board? The price
increase is negligible (at least from JLCPCB). It simplifies routing a lot and allows larger
traces for the power leads. I usually do the power and control traces on the 3rd layer -
things that will NOT be wrong.
G²
Thanks for all the support. I mentioned track widths so I agree and shall make them wider. ...1mm?
Or a ground pour so the above would be moot. I have tried adding a fill but didn't seem to work. Must look that up on YouTube
Not 100pc sure how to do tjenopsmp buffer thing but it sounds a wise move.
A lot of what has been advised to me is a little above my pay grade being very green here so I will take it away and learn. Thankyou.
Or a ground pour so the above would be moot. I have tried adding a fill but didn't seem to work. Must look that up on YouTube
Not 100pc sure how to do tjenopsmp buffer thing but it sounds a wise move.
A lot of what has been advised to me is a little above my pay grade being very green here so I will take it away and learn. Thankyou.
Hello, I worked a bit on that recently.
You might want to use your extra opamp to add a high pass filter, I had problems with sub 30Hz frequency that were amplified way to much for the driver).
You can have a look a this particular design https://jipihorn.wordpress.com/wp-content/uploads/2013/06/linkwitz-variable-state.pdf (its a Belgian guy, there is a bunch of video in french if you want, very interesting)
.
I made a little python script to compute the parameters of the linkwitz transform given its bode plot (computed by ac analysis of ltspice for instance), it's nothing releasable, but if you're interested I can give it to you
You might want to use your extra opamp to add a high pass filter, I had problems with sub 30Hz frequency that were amplified way to much for the driver).
You can have a look a this particular design https://jipihorn.wordpress.com/wp-content/uploads/2013/06/linkwitz-variable-state.pdf (its a Belgian guy, there is a bunch of video in french if you want, very interesting)
I made a little python script to compute the parameters of the linkwitz transform given its bode plot (computed by ac analysis of ltspice for instance), it's nothing releasable, but if you're interested I can give it to you
Thanks for that. I intend using on overall system high pass that is part of another active crossover so hopefully I have that covered.
So spent many hours on this taking on what has been said. I had to take inspiration from Rod Elliott's LT circuit to get my head around the buffer.
Hope this looks a bit better?!
So spent many hours on this taking on what has been said. I had to take inspiration from Rod Elliott's LT circuit to get my head around the buffer.
Hope this looks a bit better?!
Yep. R17 should connect to U1 pin 3.
It looks like your plan is to leave one of the inputs to the balanced receiver floating for 0º phase and the other floating for 180º phase. That'll be pretty noisy. I suggest grounding the unused half of the differential receiver.
I would add EMI filtering and ESD protection, especially on the input.
The local decoupling (C7, C9) should be as close to the IC pins as practical for lower inductance. Otherwise there's no point of having them on the board. The bulk decoupling (C6, C8) can be where the power enters the board.
Is there a particular reason you use Rs and Cs in series/parallel? Can you not get the values you want from the standard 1% resistors and 5% capacitors? Do you need that level of precision?
I'm not a fan of grounding anything through a mounting hole. Use a proper grounding lug. Similarly, I would not use non-plated holes for the mounting holes. I like these from the MountingHole library:
Using plated holes will ensure enough clearance between your ground pour and the mounting holes. You don't want to get a surprise connection because your mounting hardware wears through the solder mask and creates a connection where there shouldn't be one.
It's a bit odd that your ground pour is drawn outside the board. Bring that inside the Edge.Cuts layer. I usually leave 50 mil (1.3 mm) from the board edge (centre of Edge.Cuts) to any copper pour. If you bring the pour all the way to the edge of the board you can run into trouble with some connector types (SMA connectors, for example). You also then risk having your planes shorted together if the board is mounted flush with an aluminum chassis (which also isn't a good practice, but commonly done).
I'm also not a fan of connect-by-label or connect-by-netname, especially on a tiny schematic like this one. It's not a good practice as it's nearly impossible to see where the nets are connected and it's easy to miss a connection that maybe shouldn't be there. For example, I missed the 0º/180º functionality in the schematic because it isn't obvious with the connect-by-netname and also it isn't labeled in the schematic. If you absolutely can't avoid connecting by net name, use net names rather than hierarchical ports for the connections.
The only nets that I will always connect by net name is the power supply. So VCC, VEE, and GND like you have them. The schematic gets pretty unwieldy if you route the power supply everywhere in the schematic.
The schematic should be optimized for clarity. The PCB layout should be optimized for performance.
I'm not a fan of R3, R3", etc. Just number the components R1, R2, R3, .... The annotate function is handy for this. Then hit sync PCB to schematic in the PCB editor and you transfer the designators to the PCB. Currently your PCB and schematic are not sync'ed. Is that on purpose?
Your one via is tiny. I'd go with something like 12-mil (0.3 mm) hole with at least 24-mil (0.6 mm) pad. 28-mil (0.7 mm) would be even better. Just because the manufacturer can make a tiny hole doesn't mean they can do so reliably. Unless you're paying for electrical testing of your board you're better off using larger traces and holes than the manufacturer's minimum.
You could also avoid the via all together by re-routing the trace from R2" to C2".
Make sure you run DRC (design rule check) and LVS (layout versus schematic) before you submit the design for manufacturing. In KiCAD DRC and LVS are both part of the Design Rules Checker.
What you have looks decent and will probably work as designed if you move the connection to R17. You could also make it look pretty by aligning the resistors. That'll also make assembly a bit easier. I hope you're not discouraged by my detailed design review. My intent is to be helpful.
Tom
It looks like your plan is to leave one of the inputs to the balanced receiver floating for 0º phase and the other floating for 180º phase. That'll be pretty noisy. I suggest grounding the unused half of the differential receiver.
I would add EMI filtering and ESD protection, especially on the input.
The local decoupling (C7, C9) should be as close to the IC pins as practical for lower inductance. Otherwise there's no point of having them on the board. The bulk decoupling (C6, C8) can be where the power enters the board.
Is there a particular reason you use Rs and Cs in series/parallel? Can you not get the values you want from the standard 1% resistors and 5% capacitors? Do you need that level of precision?
I'm not a fan of grounding anything through a mounting hole. Use a proper grounding lug. Similarly, I would not use non-plated holes for the mounting holes. I like these from the MountingHole library:
Using plated holes will ensure enough clearance between your ground pour and the mounting holes. You don't want to get a surprise connection because your mounting hardware wears through the solder mask and creates a connection where there shouldn't be one.
It's a bit odd that your ground pour is drawn outside the board. Bring that inside the Edge.Cuts layer. I usually leave 50 mil (1.3 mm) from the board edge (centre of Edge.Cuts) to any copper pour. If you bring the pour all the way to the edge of the board you can run into trouble with some connector types (SMA connectors, for example). You also then risk having your planes shorted together if the board is mounted flush with an aluminum chassis (which also isn't a good practice, but commonly done).
I'm also not a fan of connect-by-label or connect-by-netname, especially on a tiny schematic like this one. It's not a good practice as it's nearly impossible to see where the nets are connected and it's easy to miss a connection that maybe shouldn't be there. For example, I missed the 0º/180º functionality in the schematic because it isn't obvious with the connect-by-netname and also it isn't labeled in the schematic. If you absolutely can't avoid connecting by net name, use net names rather than hierarchical ports for the connections.
The only nets that I will always connect by net name is the power supply. So VCC, VEE, and GND like you have them. The schematic gets pretty unwieldy if you route the power supply everywhere in the schematic.
The schematic should be optimized for clarity. The PCB layout should be optimized for performance.
I'm not a fan of R3, R3", etc. Just number the components R1, R2, R3, .... The annotate function is handy for this. Then hit sync PCB to schematic in the PCB editor and you transfer the designators to the PCB. Currently your PCB and schematic are not sync'ed. Is that on purpose?
Your one via is tiny. I'd go with something like 12-mil (0.3 mm) hole with at least 24-mil (0.6 mm) pad. 28-mil (0.7 mm) would be even better. Just because the manufacturer can make a tiny hole doesn't mean they can do so reliably. Unless you're paying for electrical testing of your board you're better off using larger traces and holes than the manufacturer's minimum.
You could also avoid the via all together by re-routing the trace from R2" to C2".
Make sure you run DRC (design rule check) and LVS (layout versus schematic) before you submit the design for manufacturing. In KiCAD DRC and LVS are both part of the Design Rules Checker.
What you have looks decent and will probably work as designed if you move the connection to R17. You could also make it look pretty by aligning the resistors. That'll also make assembly a bit easier. I hope you're not discouraged by my detailed design review. My intent is to be helpful.
Tom
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Thanks. I have 0.1uf from rail to GND very near IC pins. But I take it onboard and shall have a look. I kind of borrowed the ESP project ideas here.
I did have it like you mention but then when I looked back the the ESP schematic I thought I needed to change it to how it is now
Just working my way through Tom's reply. Doesn't seem to allow me to quote!
Agreed. Thinks of a schematic as carrying information 2 ways - one to the PCB editor, and the other to you. Cleaning up the schematic will help catch mistakes too.
Pay careful attention to the bypassing arrangement as mentioned above, it is very important. The geometry is what really counts.
For boards like this one, with just one or two linear chips, I typically run the power and ground in 20 to 30-mil tracks and the signals in 10-mil tracks. This makes it very easy to route between chip pins if needed, and I have never had any problems with doing that.
Depending on the final component values, you probably do not need parallel resistors, but maybe caps. I usually try to run a value sweep in my simulator to see just how sensitive the circuit really is to component variations - most have a Monte Carlo sweep that can give a pretty good prediction of how your circuit will perform in real life.
Good luck, and remember, every one of us started somewhere. I would be really embarrassed for folks to see my first PCB!
Pay careful attention to the bypassing arrangement as mentioned above, it is very important. The geometry is what really counts.
For boards like this one, with just one or two linear chips, I typically run the power and ground in 20 to 30-mil tracks and the signals in 10-mil tracks. This makes it very easy to route between chip pins if needed, and I have never had any problems with doing that.
Depending on the final component values, you probably do not need parallel resistors, but maybe caps. I usually try to run a value sweep in my simulator to see just how sensitive the circuit really is to component variations - most have a Monte Carlo sweep that can give a pretty good prediction of how your circuit will perform in real life.
Good luck, and remember, every one of us started somewhere. I would be really embarrassed for folks to see my first PCB!
Nope can't quote you Tom...
Ok yes understood on leaving the phase inversion open. Shall remedy that. And on the PSU decoupling caps.
On the series/parallel issue...I didn't know if I may need to be able to fine tune the values of the LT Rs and Cs. The calculator will just spit out ideal values that may not be actually available. Unless you think it's not necessary. I'd gladly get rid of them!
And that is half the battle I had altering all the silkscreen values to actually represent the general convention I've seen on LT circuits. So the main components being R1 thru 3 and C1 thru 3 which get repeated. Maybe I'll just let them follow the schematic designations as you say.
I don't really understand your paragraph about 'connect-by-label or connect-by-netname'. I shall have to look into this!
I think the via is 0.6/0.3mm ( my tracks are 1mm) But will double check and as you say may not be required if I rehash things again.
I do run the DRC and it is all clean bar one thing about 2 GND nets or something.
Appreciate all the feedback. It's helping me a lot.
Ok yes understood on leaving the phase inversion open. Shall remedy that. And on the PSU decoupling caps.
On the series/parallel issue...I didn't know if I may need to be able to fine tune the values of the LT Rs and Cs. The calculator will just spit out ideal values that may not be actually available. Unless you think it's not necessary. I'd gladly get rid of them!
And that is half the battle I had altering all the silkscreen values to actually represent the general convention I've seen on LT circuits. So the main components being R1 thru 3 and C1 thru 3 which get repeated. Maybe I'll just let them follow the schematic designations as you say.
I don't really understand your paragraph about 'connect-by-label or connect-by-netname'. I shall have to look into this!
I think the via is 0.6/0.3mm ( my tracks are 1mm) But will double check and as you say may not be required if I rehash things again.
I do run the DRC and it is all clean bar one thing about 2 GND nets or something.
Appreciate all the feedback. It's helping me a lot.
Oh, I see. Having component values (and labels) would have helped me understand what you were trying to accomplish. With Eliott's circuit you do indeed want R17 on the input side of R15 as you have it in post #10.
Yep. The main purpose of the schematic is to convey information to the person looking at it. Conveying information to the PCB editor is a far distant secondary purpose (in my not-so-humble opinion).
Having a schematic that's easy to read makes it easier to understand what the circuit is doing and also makes it easier to catch errors.
Now, there are some (weirdos!
) who say the schematic should mimic the PCB layout. Some even go as far as to draw custom symbols that show a top view of ICs and such. I find such an approach problematic as it obscures the circuit functionality. I would rather that the link between the schematic and PCB component placement/routing is established through layout notes on the schematic. But, of course, in the DIY world where the circuit designer and the layout designer are the same person one can skip the layout notes.Tom
I think they are?!🤔
Thanks again Tom. I think you must have been editing your post, that's why I couldn't quote.
The screenshot of the 'correct' mounting hole is very useful. I was aware my mounts didn't look quite right. Now I know why. And I hear you on the ground poor extents. I guess I was lazy and drew a box around the whole board, not considering your points raised.
I think I'll delete the series R, I believe the values available should cover it. Maybe I'll leave the C paralleled as LVQ mentions. And I'll leave all the designations on the PCB the same as the schematic.
Aren't the resistors fairly well aligned apart from R8 and R3 near the opamp? The board is for performance and so I would take that as getting things close/tracks short first and alignment second?
And absolutely not discouraged.! Quite the opposite. Thanks for your valuable time in your detailed responses. I'll spent more time on it when I get the chance. The wife kept looking quizzically at the laptop screen and said...."what ARE you doing?"!
I explained ( she is very aware of my DIY audio hobby) and she said "oh , you are clever, can you make any income out of it?"!. ( I'm soon to be made redundant from my job).
I think we all know the answer to that one!🙂
That's very likely. I always read what I wrote after I click Post Reply and often go back to add precision or further explanation. And as you've probably noticed I can be a bit long-winded at times.
R3 and R7 aren't aligned with the rest (referring to Post #10). You could scoot the resistors in the lower right over a bit to make everything fit.
I recommend turning the fab layers off, by the way. That'd be F.Fab and B.Fab. Fab stands for fabrication, not fabulous, by the way.
Just click the eyeball next to the layer name in the navigator. That way you won't see double when you move your component designators around.The only layers required for a one-up circuit board are:
- Copper layers
- Solder mask layers
- Silk screen layers
- Board outline (Edge.Cuts in KiCAD).
- Drill file(s)
Background info:
The Fab and Assy (assembly) layers are almost never used anymore and you don't have to worry about them if you're having individual boards made (what's known as one-up). In fact, KiCAD doesn't even support the Assy layer, but other softwares might. I only use the Fab layer for the panel drawing.
I generally have boards made in panels of 5-25 boards. The panel has a waste rail along the sides for handling and the boards are separated by a V-score that goes almost all the way through the panel. This way my assembly folks can load a panel of many boards into the pick-n-place machine in one shot rather than feeding the machine one board at a time. The panel approach saves money in assembly as less manual labour is required. Once the boards are assembled they are separated by snapping the V-score much like you'd break a square off a sheet of chocolate.
I've never had to use the Assy (Assembly) layer. I think it was originally intended as the assembly guide for manual assembly. The assembly folks would plot (remember plotters?) the assy layer on a large sheet or roll of paper. The graphics of the layer would be enlarged but the text kept at its original size allowing for a readable, large scale assembly drawing to be created and followed by the assembly folks.
I've never had an assembly house require such an assembly drawing. Instead they follow the component placement file which contains (X,Y) coordinates of each component.
Tom