Amp design is borrowed from an old D Self design with newer transistors which are currently available from DigiKey.
QSPICE simulations Sine Wave and Square Wave are good but not Bode. I'ts unstable. After much failed 'twerkulation' to move poles and zeros, I've chosen to seek suggestions from those with more experience. Suggestions welcomed.
QSPICE simulations Sine Wave and Square Wave are good but not Bode. I'ts unstable. After much failed 'twerkulation' to move poles and zeros, I've chosen to seek suggestions from those with more experience. Suggestions welcomed.
Attachments
Thanks for input. Bias for this design takes place with R9 & R10. R12 & R17 could be left out.
Unfortunately, it plots just the same with suggested adjustment.
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I wonder if your simulation is correct. What method do you use for loop gain analysis, which of the two simulation plots is supposed to show the loop gain and are you sure that your simulator reports phase in radians? All simulators I ever worked with reported it in degrees, but then again, I never used QSPICE.
If your amplifier is stable for small excursions in a transient analysis, it should normally also be stable in a loop gain analysis. The only exception I know is when you transient-simulate a circuit that is at the edge of oscillation with an integration method with numerical damping.
If your amplifier is stable for small excursions in a transient analysis, it should normally also be stable in a loop gain analysis. The only exception I know is when you transient-simulate a circuit that is at the edge of oscillation with an integration method with numerical damping.
Thanks.
This is the method QSPICE forum help affirmed. Confirmed on sample test circuit.
LT SPice users will use 'plot vdb(2) vp(2)*180/3.14159' which doesn't work in QSpice GUI
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base/emitter voltage goes over 1.5V
My design gives 650V when R4 is a trimpot set to 490 ohms
I don't think phase issue is caused here but I'm still learning.
You should notice that your open loop simulation has -70 db gain. You are surely not in a linear region. Your output is likely at the high or the low rail.
23-12-Bode.PNG looks perfect except for the weird phase (assuming it is the closed-loop response from input to output, which it must be because the other is called "open-loop"). 23-12-Bode_open-loop.PNG makes no sense at all to me.
The loop gain determining methods I have heard of are the loop cutting method, the method used in the asymptotic gain model, the Middlebrook method and the Tian method. The first tends to be inaccurate and may require you to modify the circuit such that biasing stays normal, the second requires you to choose a controlled source somewhere and the third and fourth require you to put a loop gain probe in the circuit.
Did you cut anything, choose a controlled source or place a probe? If so, where did you do that? The schematic only shows a simulation set-up for the closed-loop response, as far as I see.
If you did cut the loop, what did you do to ensure the biasing remains correct?
The loop gain determining methods I have heard of are the loop cutting method, the method used in the asymptotic gain model, the Middlebrook method and the Tian method. The first tends to be inaccurate and may require you to modify the circuit such that biasing stays normal, the second requires you to choose a controlled source somewhere and the third and fourth require you to put a loop gain probe in the circuit.
Did you cut anything, choose a controlled source or place a probe? If so, where did you do that? The schematic only shows a simulation set-up for the closed-loop response, as far as I see.
If you did cut the loop, what did you do to ensure the biasing remains correct?
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Your output transistors are rated at 230v. How are you getting 650v anywhere unless you are talking about an ac gain of 650.
No. Poles and zeroes only apply when a circuit is linearly biased.
Do you mean in an AC analysis or in the operating point?
You can get huge voltages out of an AC analysis because it is a linearized analysis: non-linear effects such as clipping are not included. Hence, when the small-signal gain is 650 and you apply a 1 V input signal in an AC analysis, it calculates 650 V output voltage.
If you find 650 V in a bias point (operating point) analysis while the supply is much smaller than that, then something has gone wrong.
Agh! I need to sleep - then I can type without mistakes....from VAS 650mV base to emitter - 5.1mA across each resistor R9/10 - 50+mV base to emitter to output devices
I might have identified the cause of the weird measured Bode plot - I simply expected the QSPICE directive/expressions I assigned to produce what I was looking for. I am now thinking that I need to place the probe on specific nodes. Is this deduction correct?
Trying this in LTSpice, there's definitely something wrong with the output stage biasing. I'm using KSC1845 and KSA992 for small signal but it should be pretty similar. If I want ~100 mA through Q6/Q4, I need R4 = 1k5, but then the current through Q8/Q9 is ~70 mA, clearly excessive. Try making e.g. R9=R10=100 and R4=1k15, which gives ~100 mA through Q6/Q4 and ~7 mA through Q8/Q9, much more reasonable. Having done that, I get a rather healthy PM of 70 deg and if you remove R2/C14, even better at 83.5 deg.
The easiest way to simulate the open loop gain is to put an AC signal source in series with the output sensing circuit. This allows the DC bias condition to remain intact while running the AC analysis. Then the loop gain will be the (Voltage on one end of the AC source)/(Voltage on the other end of the AC source). The phase is then the difference between the phase measured at both ends of that AC source.
Thanks, I'll try this. I've also got Spice models for those drivers you tested with.