No, I have the older part AD9687, specs differ only marginally.
Clock with and without shield.
I was lucky to have a transformer cover that fits exactly my oscillator pcb 🙂
I have a bunch of sk152, as well as the AD, and it is a RF FET, perhaps others are better ?
Is it necessary to load the oscillator with a very high impedance , the extra buffer stage could add another noise and distortion ?
If you look at the schematic, I use 1 k shunt on the input of the AD, that gave an improvement while the termination of the ECL parts was't optimal.
Now it does not seem to make a difference at all.
But I will do a listening test.
The other option that I will try later, is putting a balanced crystal filter between oscillator and comparator.
Though it looks very clean to me already.
About shielding the clock, left with shield, right without:
Without shield would be even worse if there would not be the groundplane of the motherboard shielding the solder side of the oscillator already.
This is 100 dB displayed. The sidebands are 50 Hz noise obviously.
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Can you enlighten me why that should happen ?
The setup is differential from oscillator to comparator, differential from comparator to ECL/TTL translator, single ended from ECL/TTL translator to reclocker and divider, the translator has two outputs.
I use SMB connectors between boards everywhere except here, the distance between the oscillator and the comparator is short.
Soon I will test ECL reclocking which means again differential from comparator to ECL flipflop and level translators on input and output.
Final implementation could be ECL clock drivers for the parallel DAC chips.
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I had an idea to solve the DIY DAC master - transport slave problem universally.
The clock from the DAC can be transmitted using ECL logic without problems.
On the transport side, a retriggerable monostable multivibrator disables the transport clock for a duration of two or three pulses on every incoming clock pulse.
So there is no problem of running the transport without clock.
The clock from the DAC can be transmitted using ECL logic without problems.
On the transport side, a retriggerable monostable multivibrator disables the transport clock for a duration of two or three pulses on every incoming clock pulse.
So there is no problem of running the transport without clock.
While I admire you beautiful work, I think you would do us a real favour if you could post schematics with available components.
I don't think the 2SK152 is easy to source (obsolete), and I only managed to find out about the AD96687 by accident.
Unless of course you can help us with the sourcing as well .....
😉
Patrick
I don't think the 2SK152 is easy to source (obsolete), and I only managed to find out about the AD96687 by accident.
Unless of course you can help us with the sourcing as well .....
😉
Patrick
AD96687 can be bought from Digikey.com for about 10 $.
The SK152 can be found in old Sony CD players, I think you can use the J309 like in the Kwak Clock instead.
There are other RF FETs too. Like SK120 and SK125, those even seem to be faster.
That could make it necessary to readjust the resistors 910 and 1k that set the supply voltages to about +2,5V and -2,5V.
The blue lines in the schematic that connect the left and right sides are optional and perhaps preferable, my clock has still separate supplies.
I will draw a schematic how to connect the ECL parts later.
The SK152 can be found in old Sony CD players, I think you can use the J309 like in the Kwak Clock instead.
There are other RF FETs too. Like SK120 and SK125, those even seem to be faster.
That could make it necessary to readjust the resistors 910 and 1k that set the supply voltages to about +2,5V and -2,5V.
The blue lines in the schematic that connect the left and right sides are optional and perhaps preferable, my clock has still separate supplies.
I will draw a schematic how to connect the ECL parts later.
My apology. I misunderstood my friend's points.
Bernhard, where did you get the black cover above ?
Bernhard, great work and I must say i'm quite interested. the obscene prices charged for some other discrete clocks is prohibitive, well rather I refuse to pay them. anyway i'm keen, but i'm also quite interested in your teflon PCB, can you enlighten me as to how this process is achieved?? i'm designing a transformer output PCB for my sabre dac using lundahl iron, would love to make the PCB teflon
I had a look at the clocks that are used in CD players.
Seems the biggest problem is broadband noise.
inverter clock:
crystal on old SM5807:
my clock for comparison:
Seems the biggest problem is broadband noise.
inverter clock:
crystal on old SM5807:
my clock for comparison:
Google found this:
Artikelschnellsuche der SEGOR electronics GmbH, Berlin
For the comparator there is also the single version AD9685.
If somebody needs more than one output from the clock, splitting after the comparator is no problem. Perhaps even better.
If you want to do ECL reclocking, look also for MC10124 and MC10231 and get 2 x MC10125.
The AD9687 should be soldered or plugged in single pin sockets so that it is close to the pcb. The IC gets real warm and should have heat dissipated over the pcb. Normal IC sockets are not so good...
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Schematic in post #33 is completed.
Both schematics are working, however a few part values could be optimized in future.
I have a few NOS AD9687 if somebody wants to built and can't get the chip.
7 EUR + shipping each.
Both schematics are working, however a few part values could be optimized in future.
I have a few NOS AD9687 if somebody wants to built and can't get the chip.
7 EUR + shipping each.
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Perhaps you would care to explain why you chose to use AD9687 + MC10125, instead of a single AD8561. I know the AD9687 is better in tpd, but then you need the MC10125 to get it back to TTL, and that surely adds jitter ??
Patrick
Patrick
Because I like the shiny golden package of the AD9687. 🙄
I think the sine to square conversion is very important.
Also there are more modern and faster translator chips like the 10H125.
Once you have built the clock you can always upgrade, the chip is pincompatible. Or use it from the beginning.
Another Advantage: If the clock is not very close to the rest of the DAC, you can put the 10125 close to the DAC chips and have a differential terminated transmission line.
Onsemi states that CMOS adds 10 ps jitter per chip while ECL stays below 1 ps.
That is the reason why as mentioned before, I have started building a ECL reclocker with a ultrafast flipflop that again allows to use a differential terminated transmission line and convert to TTL/CMOS in front of the DAC chips.
ECL in any case offers the lowest jitter of all logic families and avoids ground bounce problems found with cmos.
74HC74 has 90ns propagation delay while a 100E131 has 0,5ns propagation delay, allows a toggle frequency of 1,4 GHz and the datasheet claims < 1ps random clock jitter.
Why ruin everything with a garbage flipflop ?
ECL from the beginning guarantees lowest jitter all the way down to the DAC chips.
There are also 1:8 ECL to TTL clock distribiution chips available for my parallel chips, that solves another problem elegantly.
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IMHO the differential design also doubles the effective slew rate of the sine wave seen by the comparator inputs.
AD8561 also works with the differential clock. I like the idea of the diff clk, very much.
But yes, good arguments with ECL. You talked me into it. 7 Euro is also fair.
What is the difference then to the more modern AD96687 ?
Maybe we should exchange notes by PM.
You just managed to get me to rethink the whole architecture.
BTW I used to live in Munich, but now 2,5 hours drive away (nicht ganz freiwillig....).
Cheers,
Patrick
But yes, good arguments with ECL. You talked me into it. 7 Euro is also fair.
What is the difference then to the more modern AD96687 ?
Maybe we should exchange notes by PM.
You just managed to get me to rethink the whole architecture.
BTW I used to live in Munich, but now 2,5 hours drive away (nicht ganz freiwillig....).
Cheers,
Patrick
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