Hello,
in addition to my Headphone Amp I want to design a DAC board with SPDIF input (44,1-192kHz) with the ES9039Q2M in HW-mode. I am not an electrical engineer but was successful with some smaller projects with KiCad and I'm asking for a bit of support.
I started with the design based in the datasheet:
Best
Florian
in addition to my Headphone Amp I want to design a DAC board with SPDIF input (44,1-192kHz) with the ES9039Q2M in HW-mode. I am not an electrical engineer but was successful with some smaller projects with KiCad and I'm asking for a bit of support.
I started with the design based in the datasheet:
- At the moment I only have +24V available, what would be the recommendation to get +5V? (LM337/LM7805..)
- What voltage is needed for the opamps (OPA1612)?
- Some values for C are not clear for me from the datasheet (marked with ???)
- In the datasheet it says "For S/PDIF in HW mode, DATA7/GPIO7 is the S/PDIF stream input" and in table 5 GPIO 4 is stated. Which one is correct?
- Is the Crystek CE3391-49.152 a good compromise for 44,1-192kHz?
Best
Florian
Some people don't seem to be too keen on the ESS LDO. Also, don't know that its such a good idea to avoid I2C register programming.
Don't know why you want SPDIF input only. A lot of times dacs sound better with USB and fully synchronous dac operation. Thus, wondering how much of an issue perceptual sound quality is for you?
In addition, it can depend a lot on how a dac board is physically laid out, how many PCB layers are used, what it used to provide external power, etc.
Regarding Crystek CE3391, wondering where you would find that, as Mouser and Digikey don't seem to stock them? Also wondering why you would choose that part as there are probably better choices.
Also wondering what type of capacitors you are thinking of using for C5 and C16?
The I/V opamps usually run on something like +-15v, although a little lower could be okay too. If you only have 24v dc available, would you want to use a DC-DC converter to make a negative voltage rail for the opamps? If so, that can be tricky. SMPS can generate electrical noise that can cause SQ problems, especially a risk for inexperienced designers.
Don't know why you want SPDIF input only. A lot of times dacs sound better with USB and fully synchronous dac operation. Thus, wondering how much of an issue perceptual sound quality is for you?
In addition, it can depend a lot on how a dac board is physically laid out, how many PCB layers are used, what it used to provide external power, etc.
Regarding Crystek CE3391, wondering where you would find that, as Mouser and Digikey don't seem to stock them? Also wondering why you would choose that part as there are probably better choices.
Also wondering what type of capacitors you are thinking of using for C5 and C16?
The I/V opamps usually run on something like +-15v, although a little lower could be okay too. If you only have 24v dc available, would you want to use a DC-DC converter to make a negative voltage rail for the opamps? If so, that can be tricky. SMPS can generate electrical noise that can cause SQ problems, especially a risk for inexperienced designers.
Last edited:
I would like to use it with a streamer that only has an SPDIF output. Maybe I add USB/IIS later, but this is my main goal.
If possible I want to avoid having a MCU on the PCB for register programming for noise reasons. What registers should be set?
For the Crystek CE3391 I see 700 in stock at mouser (for the 49.152 MHz version). The sometimes recommended types from NDK are end of life, what would your recommendation be?
For the caps I will probably go for C0G/NP0, haven't decided for the exact type yet.
Is there an alternative for supply of the opamp? For this design I would like to avoid a transformer/mains to keep the enclosure size low.
For example a DCDC converter with added LDO?
For power, maybe something like this would work: https://www.digikey.com/en/products/detail/mean-well-usa-inc/GP50A13D-R1B/7703343
An MCU can set the registers for DPLL_BW which can affect SPDIF sound quality, and registers for digital volume control. Maybe some other registers would be of interest too. MCU could go on bottom side of dac board to help isolate it from the sensitive circuitry, and I2C bus isolator chips are available to help control conducted noise.
Crystek CD3391 is a "standard" oscillator, not a low-jitter one for higher quality audio. Also, I don't use ferrites in the power to my clocks. I find ferrites can be designed around and when they are used I don't like what they do to the sound. There is some more info on ferrites in my Clock Board thread. Also, clocks are just as important as low noise AVCC voltage regulators. All dacs need a good analog time reference and a good of analog voltage reference (likely a pair, for best stereo). The clock or clocks should have very clean, low noise regulated power for best results.
An MCU can set the registers for DPLL_BW which can affect SPDIF sound quality, and registers for digital volume control. Maybe some other registers would be of interest too. MCU could go on bottom side of dac board to help isolate it from the sensitive circuitry, and I2C bus isolator chips are available to help control conducted noise.
Crystek CD3391 is a "standard" oscillator, not a low-jitter one for higher quality audio. Also, I don't use ferrites in the power to my clocks. I find ferrites can be designed around and when they are used I don't like what they do to the sound. There is some more info on ferrites in my Clock Board thread. Also, clocks are just as important as low noise AVCC voltage regulators. All dacs need a good analog time reference and a good of analog voltage reference (likely a pair, for best stereo). The clock or clocks should have very clean, low noise regulated power for best results.
This is the (v2 = improved) output stage from the ESS data sheet:
I understand that thevalues of the components around the op amp are no longer critical to avoid the hump, and no published data of 9039 DACs that I have seen exhibit the hump.
Does anyone know what the three op-amp version with slightly improved THD+N looks like? I the third op-amp maybe just for buffering the reference voltage, as a symmetrical output should have an even number of amps?
Is there a simpler way to get unbalanced output? Just using one side of the symmetrical output signal seems odd. The Chinese...
Does anyone know what the three op-amp version with slightly improved THD+N looks like? I the third op-amp maybe just for buffering the reference voltage, as a symmetrical output should have an even number of amps?
Is there a simpler way to get unbalanced output? Just using one side of the symmetrical output signal seems odd. The Chinese...
GPIO4 Input S/PDIF input in HW mode (HW modes 16-18)
GPIO7 Ground Must be connected to Ground in HW mode (Pin 27)
And then look at 16-18HW modes in table to configure HW pins to GND/AVDD or pull-up to AVDD or pull-down to GND.
Last edited:
Hi! I am actually designing this DAC, could be intresting for you….
Forgot to mention it might be worth adding a pulse transformer to the SPDIF input in order to break any AC line ground loop with the streamer.
Unfortunately:
🙁 But even if it would be available I would like to avoid components which are too special, at the moment only a 24V DC source is planned to be connected to the enclosure (a class a headphone amp will also be in there).
You are right, unfortunatley only lower frequency versions:
Would that be the recommendation?
This is the (v2 = improved) output stage from the ESS data sheet:I understand that thevalues of the components around the op amp are no longer critical to avoid the hump, and no published data of 9039 DACs that I have seen exhibit the hump.
Does anyone know what the three op-amp version with slightly improved THD+N looks like? I the third op-amp maybe just for buffering the reference voltage, as a symmetrical output should have an even number of amps?
Is there a simpler way to get unbalanced output? Just using one side of the symmetrical output signal seems odd. The Chinese...
GPIO4 Input S/PDIF input in HW mode (HW modes 16-18)
GPIO7 Ground Must be connected to Ground in HW mode (Pin 27)
And then look at 16-18HW modes in table to configure HW pins to GND/AVDD or pull-up to AVDD or pull-down to GND.
Thanks, my datastheet of ES9039Q2M (newest version 0.2 from their website) looks a bit different, some caps seem to be not needed.
I connected the pins so it should be in HW mode 16. Is this correct? When you look at the footnote 1 for HW mode 16 it says "For S/PDIF in HW mode, DATA7/GPIO7 is the S/PDIF stream input" in table 5 it says GPIO 4 🙄
Hi, definitely! Haven't seen this thread before.
Sorry I should have been more precisely, its S/PDIF over toslink 🙂
Looks like diyinhk has the clocks: https://www.diyinhk.com/shop/audio-...-frequency-49152mhz/113-magnifier_option-null But if you don't like that one, Crystek does make some clocks suitable for dacs, CCHD-957 being a well known one.
Also, the power supply isn't that rare: https://trcelectronics.com/products...by5LuAR4MYOHvYT7TpYLnOBnM0nYoXBRoC6lIQAvD_BwE
Meanwell is a very reputable brand often used in audio equipment due to its low noise. Unlikely you could design a DC-DC converter as good, given that you are pretty new to this.
Also, you did ask for some advice and or comments regarding what you are trying to do. You have now been getting some good advice from some pretty experienced people, but you are certainly free to ignore it if you like.
Also, the power supply isn't that rare: https://trcelectronics.com/products...by5LuAR4MYOHvYT7TpYLnOBnM0nYoXBRoC6lIQAvD_BwE
Meanwell is a very reputable brand often used in audio equipment due to its low noise. Unlikely you could design a DC-DC converter as good, given that you are pretty new to this.
Also, you did ask for some advice and or comments regarding what you are trying to do. You have now been getting some good advice from some pretty experienced people, but you are certainly free to ignore it if you like.
Last edited:
Perhaps there is a mistake in one version, but both versions claims that GPIO7 Ground Must be connected to Ground in HW mode (Pin 27). Contact ESS
If to select right MCU, it's noise is less than the noise from the AC itself.
Alex.
Got it! I’ll add some breakout pins to allow connecting an MCU if register adjustments are needed.
I was hoping to save some cost with a cheaper Crystek version, but if this is the recommended choice, I’ll go with it. I also try to source components from suppliers that PCB assemblers with pick-and-place machines can easily purchase from—especially for parts I prefer not to solder myself to ensure consistent quality.
Absolutely, I’ve used their products many times, including a 24V PSU for the amp in this setup. The challenge for me is either adding a second PSU or redesigning the amp, which is a bit of a headache.
I really appreciate the valuable advice and shared experience! My goal isn’t to dismiss any input—I'm asking follow-up questions to better understand the reasoning behind certain recommendations. I genuinely want to learn and make informed decisions. Thanks for your patience!
Hi, I updated the schematic:
- Added clock CCHD-957
- Added possbility two switch between this clock and CE3391 (I am curious I am able to hear a difference with my equipment)
- added an extra LDO for the clocks
- Added LM317 for +5V (from +24V DC)
- Added Meanwell DPBW03F-15 for +-15V (from 24V DC)
- fixed output stage acc. EVB v2.1
- added HW/SW mode switch
- added mute switch
- added possibility to access the I2C lines
- added TPA6120 as headphone amp (the discrete class a design will be added later)
Before looking at details, I might just mention that some people here in the forum feel that CCHD-957 (for whatever reason) tends to sound subjectively better with a particular bypass cap, which needs pads a little bigger than the standard 805 smd size. The bypass cap is a 0.22uf Rubycon MU, part# 16MU224MZ22012 Not cheap, but IME definitely worth trying.
Also, the CCHD-957 should be left running at all times for lowest phase noise. It may take a few days of running to settle into its most stable operation.
Besides bypass caps, the clocks should probably also have series damping/termination resistors. May not be needed if they are close enough to the dac load, but sometimes it helps to layout the clocks in a strategic location where ground plane currents flowing under them are minimal.
In addition, commonly we would label caps which are C0G/NPO as such the schematic (such as the output stage small value filter caps).
Also, the CCHD-957 should be left running at all times for lowest phase noise. It may take a few days of running to settle into its most stable operation.
Besides bypass caps, the clocks should probably also have series damping/termination resistors. May not be needed if they are close enough to the dac load, but sometimes it helps to layout the clocks in a strategic location where ground plane currents flowing under them are minimal.
In addition, commonly we would label caps which are C0G/NPO as such the schematic (such as the output stage small value filter caps).
Last edited:
I am not sure that the ES9312 Vregs the best solution for this function are, especially for the clock! Don't forget DVDD with 1.2V!
Last edited:
Thanks, I will add the the rubycon capacitor. Is 50 Ohm for the series resistor okay?
Do you also have an overall capacity of around 220nF?
Last edited: