ESS Sabre Reference DAC (8-channel)

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#2,703
9039 is up and running now. It was a misstanke in registers.
I did use a basic setting for SPDIF (optical) and dac works perfect.
For now a more basic outputsstage without a servo that ESS has in the datasheet.
I use the same stage as in the 9038 with vref at 1.65v from avcc/2.

Thanks.

BR// Daniel
 
#2,704
@Green77 do you remember what did you have to change in registers to get it working?

I have ES9039Pro in 8-channel mode using TDM input, slave and async. So quite a bit different configuration, but anything can help 🙂 I have been shuffling the register bits couple of days now but no luck… I’m working on setup where I can change registers easier as well as read the status registers to get a hang of it. Now it has been just compiling the controller code over and over again if I want to change something, which has been quite tedious..

Datasheet mentions an app note for TDM configuration. Anyone seen it?
 
#2,706
What should be the full scale output voltage with ES9039Pro with their recommended I/V stage? I got the DAC working now with 8 channel TDM signal coming from ADAU1462. The full scale output voltage I got is 7Vpp, which seems low to me considering the 900ohm FB resistors and the specified full scale current. First time working on a ESS DAC, so I'm not sure am I missing something... I'm mostly worried that the TDM format is still wrong and bits shifted or something...

I got first measurements done with E1DA ADC + APU notch and THD+N numbers looked good.
 
#2,714
Green77 said:
Thanks for your help.

I tie output togheter like this.

View attachment 1195172

I use ADM7154 for AVCC L, AVCC R and clock (50Mhz CCHD-950). Multi TPS7A20 to other 3.3V connections.
And a SPX3819M5-L-12TR for DVDD at 1.2V.
All volatge around dac messure ok and chip is found by MCU,

I did try the same outputstage as in my 3038pro, With some tweaked value.
View attachment 1195176
It works perfect in the 9038pro in stereo mode .
You think it can't handle the 9039pro in stereo setup? With 4 output tied togheter?

As for the startup of program:

Set register 0 bit 7: 1
wait 400 ms
Set register 0 bit 7: 0

Set register 0 to: b00101110

Set register 1 to: b10111111

Set register 3 to: b10000000 - Also tryed b0000000 - Don't know if AUTO_FS_DETECT should be enable or disable??

Set register 123 to: b00000000 - Disable automute

As i said before, DPLL locks to input signal.

BR// Daniel


Click to expand...
how to get the samplerate?couldn't find the relevant register.
 
#2,717
Okay, then you have to calculate it, as I said. The dac chip doesn't know what frequency clock you used, only you know that. So that's why you have to do the calculation.

Which register you get DPLL_NUM from may vary with the particular ESS DAC part number you are using. Look in the datasheet. There is formula that relates clock frequency to incoming audio sample rate.
 
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#2,719
Not sure if there is a way with ES9039. They may figure it doesn't matter as the ASRC will take care of the SPDIF stream automatically. If you really have to know for some reason you could use an external SPDIF receiver, maybe such as AK4118 (in which case if AK4118 is fitted with a local crystal, it can determine the incoming sample rate).
 
#2,720
Based on ES9039Q2M datasheet register 251 can be used to read a byte of SPDIF payload (presumably channel status). The byte to read is set in register 136. The structure of channel status bits can be found from ES9038Q2M datasheet (register 70-93). Sample frequency is in byte 3 of channel status. Note that I haven't tested this so it is only my assumption.
 
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