I know 🙂 And there is the adjustable delay of +/-32k steps of 1/(256 * F_VCO) => 0.3ps independently at each output (this feature was removed from the docs due to instable consistency at high temperatures) which is great for compensating skews on I2S lines at high samplerates.
Most fixed crystal clocks will measure better, but the Si5340 flexibility wins hands down in my use case.
I somehow fail to follow your course of reasoning...
This is 768kHz zero signal DAC -> ADC loopback clocked by Si5340 - the peak at 54kHz is switching frequency of a cheap SMPS adapter powering the rig, the highest bin is some REW processing artefact - not many people test REW at these samplerates:
And 350kHz @160db (i.e. below the 24th bit) sent to the DAC (apparently the 4M FFT statistics drills down to tiny signals):
I do not claim these are SOTA results but the clock performance is OK for me. Compare with other ES9822 768kHz measurements available on this website and elsewhere.
But again - this thread is about I2S, not clocks.
That is looking at noise floor, not close-in phase noise, right?
A whole thread on how to look at it: https://www.diyaudio.com/community/threads/phase-noise-in-ds-dacs.387862/post-7063038
The programmable clocks generally have rather poor close-in phase noise, which why they sorta hide that information.
If it doesn't matter to you, that's fine too.
A whole thread on how to look at it: https://www.diyaudio.com/community/threads/phase-noise-in-ds-dacs.387862/post-7063038
The programmable clocks generally have rather poor close-in phase noise, which why they sorta hide that information.
If it doesn't matter to you, that's fine too.