Mosfet failure analysis

[jan.didden]

Troels, there is another failure effect in MOSFETs, called the Spirito effect (the guy who discovered it). It looks a bit like BJT current hogging but the cause is different.
The root cause is the slightly different Vgs values in each of the cells that make up a large MOSFET die. Especially at high Vds, these differences are increased and of course the cell(s) with the lowest Vgs draws the most current, which causes local heating, which causes nearby cells to start conducting more, etc.

There's a NASA online study on the 'net as well as some papers from Spirito and I think also an app note from IR on the subject.

Not saying this is the cause of your problems but might be a good idea to try to exclude it.

Jan

 

[Reactance]

Thanks for All the great input. Il get back to you in a Day or two.

Kind regards TroelsM

Forgot to link this, a beautiful app note.

Zener Theory and Design Considerations Handbook


Page: 27
HIGH FREQUENCY AND SWITCHING CONSIDERATIONS

At frequencies about 100 kHz or so and switching speeds
above 10 microseconds, shunt capacitance of zener diodes
begins to seriously effect their usefulness.

https://www.onsemi.com/pub/Collateral/HBD854-D.PDF

Have fun.

 

[TroelsM]

My impressions of the schematic, the MOSFET driver section:


Well its not the recommended circuit from the IR2184 datasheet is it? I can't see anything to stop Vb-Vs exceeding 12V (pins 8 and 6) as there is a dodgy looking leakage path from the HT via R30 and R32 to the Vb. That alone could pop the top MOSFET..

No, the IR2184 is not meant for classD at all, but its cheap and easy to get. The idea with R30 and R32 is to provide a constant "DC bias" for the HS-drive under all circumstances, including heavy clipping. A zener from pin 6 to 8 may be a good idea for the next version.

R52 strains the bootstrapping circuit by imposing a DC path to discharge the floating cap C24, which is clearly why R30 and R32 were added - alas that's not how these chips are designed to operate.

R52 and R60 are pretty common in HB-switch application. I dont really think they make much difference for this application, but they do keep Vgs under some control during assembly and testing.

C24 needs to be ceramic multilayer to handle the high speed current requirements (dI/dt here can be of the order of 10^7 to 10^8 A/s). C24 only needs to be about 10 times the MOSFET input capacitance if there's no other load, but must be very low inductance, an electrolytic or film cap will not do.

C24 is a electrolytic right now and although it does work, it may not be ideal. I dont agree that the cap can be as small as you say. under heavy clipping the cap needs to store enough energy to keep the HS-mosfet fully on så it does not go linear and heat up. Yes, we should avoid heavy slipping and I will implement a limiter.

T5 and T7 are presumably designed to speed up switch off compared to switch on. This isn't likely to work (MOSFET gate driver chips can source and sink large currents - more than an amp in a fraction of the time T5 or T7 can switch off). Stored charge in these devices could be playing havoc with the switching. A simple schottky across R42 and R57 would not have this problem if asymmetrical was really important.

I'm not sure that T5 and T7 are really necessary, but I had room for them. the schottky//resistor-solution are more common and maybe it would be better. I really dont know

C22 and C24 need to be right on the chip's pins, a few mm away at most, and all the high speed high current gate path needs to be tightly laid out for minimum inductance, my favorite way is to route the gate current path over the returning source current path on a 2-layer board to minimize loop area and keep the fields mainly inside the PCB laminate.

C22 could be closer to the driver. C24 is 3mm away. Loops will be even better in the next version, but I only have 2 layers to work with and a tight layout.

If there is any distance between driver and MOSFET add a 15V protection zener across gate/source to clip any inductive ringing.

There is a total of 20mm to each mosfet. Iøm not sure that a typical zener is fast enough to actually clip 1Mhz ringing??

C21 looks totally wrong, the switching waveform needs to be crisp.

If implemented C21 should be so small that the basic waveform is clean. If the signal is noisy, then C21 can clean the edges a little. I dont use C21 in this version

 

[TroelsM]

There seems to be a misconception that a zener at the Vgs for clamping protects against high dv/dt , this is NOT true, the zener in question is used for slow gate Vgs signals, however here we anticipating to clamp signals in access of 100MHz leaking in and out from the power fets (via its parasitic capacitance) into gate and to the IR driver. The gate's thin channel will probably fail (no heat required here)

OK, makes sense. The typical zener on GS is implemented to limit static "DC" Vgs above the limit.

TVS high speed clamp diodes exists for this reason, but doesn't apply here, cause the currents in question are too high, it wont help with the real problem and there are many.

1) +/- 70V that IR + single transistor drive circuit is very mediocre.

Can you suggest a better alternative? Looking at other solutions in similar designs, I see the same basic setup over and over.

2) LM311D PIN 7 and 6 can be connected together to improve propagation delay speeds.

Nice, I'll try that, but I dont think that delay is my biggest problem right now.

3) The gate pull-down resistor 4k7 seems very low, 100k is fine.

OK, It works now, but next version could use a bigger resistor.

5) Probably worse and most complex: The output has two loops, one post the other pre-feedback, here lies many problems and interesting research and improvements.

Yes, there are 2 loops, and I'm not a feedback specialist. R1-R8-R13 and R21 is the "inner" feedback that keeps the amp oscillating. and provides basic feedback. With this loop I get around 0.1% THD.
C1, C5, R6, R16, C12 and R10 provide a PFF that can do 2 things: lower THD to approx 0.02% (best case) AND maybe more important for this application: tame the overshoot at the output, especially if the load is removed

a) The carrier residual from the output (pre-stage) feeds directly into the input of the TL072, using poles and zeros lead/lag networks, you can actually simulate this independently in a simulator and see how she behaviors. The main thing I can see here is output before the filter has spectral content/noise way too high for that OPAMP to handle and probably results in failure line noise can even make it fail, who know what that network's behavior looks it, only a bode plot can show you. Consider researching compensation topics, Type I, II, III and get some understanding how important control stability is. The same goes for the post loop, only this time the loop is taken after the filter, so here too that loop needs to be analysed.

I have simulated the feedback behavior, but I'm limited in my control-theory ;-)

Part of your modulator design is very common in class-d car audio amplifiers, with failure at random like yours did, International Rectifiers first generation class-d prototype reverberates 10 years later.

OK. It would be more helpfull if you could clearify that som emore.

 

[SemperFi]

You've got many good tips so I aint gonna try too hard.
The driver network with the pnp for level shifting down to the neg rail...cannot be very fast? Get a real driver man.
As mentioned by Mark the bootstrap HS driver cap needs to be a small and fast ceramic. This cap is critical.
Also, the Vboost cap C24 is charged from the driver's supply rail, as in the closest decoupling cap, C22 I guess. So since C22 is both driving the low side gate, and charging C24, it needs to be larger than 47nF. But not too big b/c you want C22, and C24, to be effective over several MHz. A good 1uF ceramic is barely decent up to 2MHz if it is mounted and placed properly. Layout is critical.
Unfortunately the MOSFETs used are heavy slow suckers to drive, So you need several hundred nF. I'd start by trying 470nF to 1uF for C24. Increase R52 and R60 to 10kohm and 470nF will hold the gate long enough. Don't clip the amp so no worries.
A charging resistor from HVrail to HS driver cap ,R30 and R32 in your schem, is sometimes used but if so you must have a zener, 12V or so, across C24. Also balance it with same resistors and zener from VS to COM (on the driver).
With those MOSFETs the amp is no good for 4ohm, it just isn't. Too high Rds on.
Those MOSFETs have horrid body diodes (man why use such effort and waste it on horrible MOSFETs?)
Btw a trick to eliminate the body diodes is to place a good fast diode in series with the drain, then a smaller faster diode across both MOSFET and series diode, but opposite direction. The recovery of proper fast diodes is so much better than the body diode. The diode in anti parallel can be very small, 1A or so, with smallest recovery time, since the currents going up that way are very short spikes.
running out of time...need to run. I'm a slow talker, sorry. But one last thing: layout is critical. think signal and return, they must be close and intimate. The driver signal to gates and their returns back to driver, vias connecting ceramic caps must be placed tightly together, on inside of the pads, etc.