Phase margin and gain margin are usually extracted at the amplifier output before the output coupling inductor network. Without it, it doesn’t take a feedback amplifier much capacitive load to prompt it into oscillation, or peaky response behaviour.
However, with even a small inductor (0.5 to 1uH), very effective isolation of the load is provided. I regularly test my designs with capacitive loads of up to 2.2uF without any problems. Is 45 degrees of PM enough. Normally I design for 60 degrees, use an output L of 0.5-1uH and TMC compensation, but with a suitable output L, PM’s of 45 degree are also ok. You could not do this without an output L. Its important BTW to ensure you have good gain margin as well. With TMC, figures of 10-20 dB are normal. 😊
https://hifisonix.com/wp-content/uploads/2014/11/Output-L_1.pdf
Bonsai brings up a good point, Sevy. If you name the actual output node (after the L) "out", you need to change the node name in the loop gain formula you're plotting. For instance, in LTSpice demo circuit "LoopGain2" they name that node "x" and the LG formula used there uses "x" rather than "out". The probe and calculation is intended to measure the gain from the probe's positive end to its negative end, so the nodes you measure should be the nodes on either end of it. I used that method to get the GM/PM numbers I posted earlier.
Bias current too low?
I fitted R21 modules into a silent amp (see https://www.diyaudio.com/community/threads/an-arguably-better-replacement-for-the-resistor-in-a-crc-power-supply-r21-ps-module.376003/page-10).
After switching the amp on, I was shocked by a sizzling noise accompanied by slight whistling.
What went wrong?
By mistake I had set the output voltage of the R21 module more than 10V below its input voltage. Accordingly, the bias current of the output transistors had dropped to a few mA. Readjusting it to the original level was the cure: Complete silence again.
I fitted R21 modules into a silent amp (see https://www.diyaudio.com/community/threads/an-arguably-better-replacement-for-the-resistor-in-a-crc-power-supply-r21-ps-module.376003/page-10).
After switching the amp on, I was shocked by a sizzling noise accompanied by slight whistling.
What went wrong?
By mistake I had set the output voltage of the R21 module more than 10V below its input voltage. Accordingly, the bias current of the output transistors had dropped to a few mA. Readjusting it to the original level was the cure: Complete silence again.
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So to follow this thread, now that I have redo the PCB I am ready to redo the simulation before proceeding with it's fabrication. I started over my simulation following every steps one by one.
The original Cdom capacitor (C301/401) were 10 pF. On the Open Loop Gain, I get effectively 6.4 MHz at 0 dB, here:
In order to have Open Loop Gain at 2 Mhz at 0dB I had to raise C301/401 to 100 pF.
Now, from my understanding of the comments above, I have to check the Close Loop Gain and Margin with the formula:
So here are the results with C301/401 at 100 pF:
The cursor 1 is showing the Mag of 0 dB (31.62mdB) and cursor 2 is showing a phase of 180° (-180.3072°). The cursor 1 phase is at -93.91489° with a ratio of -86.392306° between them. My understanding would be that I have 86° of phase margin. Do I understand correctly?
If yes, 86° of phase margin is almost 90° that is a minimum from what I read. So am I safe here or should I raise a bit C301/401 to reach 90° minimum?
In the next step I want to simulate also TMC and I already have reserve PCB space for the extra capacitor and resistor for it.
The original Cdom capacitor (C301/401) were 10 pF. On the Open Loop Gain, I get effectively 6.4 MHz at 0 dB, here:
In order to have Open Loop Gain at 2 Mhz at 0dB I had to raise C301/401 to 100 pF.
Now, from my understanding of the comments above, I have to check the Close Loop Gain and Margin with the formula:
So here are the results with C301/401 at 100 pF:
The cursor 1 is showing the Mag of 0 dB (31.62mdB) and cursor 2 is showing a phase of 180° (-180.3072°). The cursor 1 phase is at -93.91489° with a ratio of -86.392306° between them. My understanding would be that I have 86° of phase margin. Do I understand correctly?
If yes, 86° of phase margin is almost 90° that is a minimum from what I read. So am I safe here or should I raise a bit C301/401 to reach 90° minimum?
In the next step I want to simulate also TMC and I already have reserve PCB space for the extra capacitor and resistor for it.
Sevey, 200 kHz ILGF is too low because it means you are throwing away high frequency loop gain and therefore the opportunity to reduce distortion. For your amp I would aim for between 1-2 MHz - so if you used 100pF Cdom caps in the above plot, try changing them to about 47-68 pF. For phase margin, it is recommended you aim for >60 deg. With an output coil (which you have), you can even go lower, but I'd just stick with >60 deg for this amp and you should be okay.
Sorry for my confusion, but I have hard time to understand what I should expect with the Bandwidth plot versus what I should expect for the Open Loop Gain plot. And to add to my confusion, I though that your comment above that 5 MHz was to high was referring to the Bandwidth while now you seem to talk about the Open Loop Gain. Also I realize that my comments and plots above are wrongly named. The first plot comment as
So how do I check the Close Loop Gain in LTSpice?
I'll redo my simulation with your suggestion above...
Isn't the Open Loop Gain plot but the Bandwidth plot. I realized that with the name of the function formula named that is "olg()". So my comment below:
The plot isn't the Close Loop Gain but is the Open Loop Gain "olg()". :-/
So how do I check the Close Loop Gain in LTSpice?
I'll redo my simulation with your suggestion above...
So back to school, I used the olg() function to plot three different Cdom values. The original 10pF design and your two suggestion 47pf and 68pF.
This is the olg() function plot for the 10pF with 1.16MHz at 0 dB:
This is the olg() function plot for the 47pF with only 294KHz:
This is the olg() function plot for the 68pF now with 206KHz:
My conclusion would be to stick with the 10pF. Do you agree?
Following the above while using TMC with C301a/401a at 10pF while varying C301b/C401b from 10pF to 33pF, I would conclude that while the Frequency raise with the C301b/401b value, the Phase Margin is lowering. My guest would be to have the highest Frequency with the highest Phase Margin. I would choose 10p/22p seeing that the Frequency doesn't raise for these values (1.6156833MHz) while the Phase Margin is better with the lower C301b/C401b at 22pF.
What do you think Bonsai?
What do you think Bonsai?
This is a quick summary of how to do a loop gain plat
If you are decreasing the ULGF (unity loop gain frequency which is where the loop gain crosses the 0 dB gain line) I would expect that you phase margin goes UP. If you set the ULGF too high, the phase margin should go down. So ideally, you want to set it between 60 and 90 degrees.
[NB in the picture above, make sure all other voltages have the AC voltage set to 0 or blank in the 'AC Small signal Analysis' dialog box]
If you are decreasing the ULGF (unity loop gain frequency which is where the loop gain crosses the 0 dB gain line) I would expect that you phase margin goes UP. If you set the ULGF too high, the phase margin should go down. So ideally, you want to set it between 60 and 90 degrees.
[NB in the picture above, make sure all other voltages have the AC voltage set to 0 or blank in the 'AC Small signal Analysis' dialog box]
Hi,
It look's like the one Minek123 has shared in preceding posts. This is how I drawed it in LTSpice, with the Input to ground and the Vi1 at 1 V into the NFB path. The above plot are made from this schematic.
Another way to do the open loop gain plot is use an LC section in the feedback path after the divider, set to 1pF and 1pH for closed-loop analysis, but 1GF and 1GH for open-loop - for open loop probe the output of the feedback network before this LC section, for closed loop the amp output of course. Thus you only have to change component values between open- and closed-loop AC analysis, basically it acts as an AC switch that breaks the loop at the inverting input of the amp.