Thought I'd start a thread for this. I am into another amplifier design. This time its on strip board. And I'm likely to have many more odd questions.
It's basic topology is a diamond front end, beta enhanced VAS, HEC output stage with one pair (currently) of vertical MOSFETs. Compensation is TMC.
First question is whether it is possible that having too low ULGF can cause instabilities in itself? Or having too much closed loop gain? Using Tian probe I have a main loop ULGF of 600Khz and a closed loop gain of 30dB. In this configuration if I have the output stage biased above 0mA or voltage rails above 35v it breaks into oscillation. If I cut the feedback shunt resistor it stops oscillating and can have OPS bias and 60v rails. If I decrease the closed loop gain by increasing the feedback shunt resistor then it is stable again but the ULGF increases (800Khz). Don't understand this I thought having a low ULGF would be less problematic.
Second question is that with TMC the loop gain plot has a shelving just above the ULGF which kills Gain Margin. Switch to TPC and the shelving disappears and gain margin is massively improved. Is TMC incompatible with the HEC output stage?
Thank you
Paul
It's basic topology is a diamond front end, beta enhanced VAS, HEC output stage with one pair (currently) of vertical MOSFETs. Compensation is TMC.
First question is whether it is possible that having too low ULGF can cause instabilities in itself? Or having too much closed loop gain? Using Tian probe I have a main loop ULGF of 600Khz and a closed loop gain of 30dB. In this configuration if I have the output stage biased above 0mA or voltage rails above 35v it breaks into oscillation. If I cut the feedback shunt resistor it stops oscillating and can have OPS bias and 60v rails. If I decrease the closed loop gain by increasing the feedback shunt resistor then it is stable again but the ULGF increases (800Khz). Don't understand this I thought having a low ULGF would be less problematic.
Second question is that with TMC the loop gain plot has a shelving just above the ULGF which kills Gain Margin. Switch to TPC and the shelving disappears and gain margin is massively improved. Is TMC incompatible with the HEC output stage?
Thank you
Paul
Time to make use of this thread again.
Having problems with oscillation with Bob Cordell's Hawksford Error Corrected output stage. Using Cascoded drivers as per version in Bob's book. I like to use the BC3x7 devices. The output devices are 4 pairs of IRFP240/9240.
The oscillations start when I try to bias the output stage. Anything between 10mA and 100 mA per pair causes oscillation.
I have 100R gate stoppers and 100uF decoupling right at the drain pins. The cascoded drivers share the same rails as the MOSFETs. The decoupling caps have separate ground lines back to the PSU star point. The rest of the amplifier runs off separate power lines back to the bench PSUs. All this is built on stripboard so layout is massively compromised. If I try to add Gate to Drain caps (to one FET in particular) the oscillations get much much worse and the PSUs go from 28mA to 1.5 Amps draw where the current limit is set.
When I scope the rails there is about 500mV peak to peak oscillation visible in the 10Mhz. The gates are also oscillating at about 1V peak to peak. The ground lines back from the decoupling also show 500mV oscillation. Putting 1R+1u snubbers on the power rails doesn't help. Adding film caps didn't make any difference. The wires going back to the PSUs are very skinny (20 AWG).
There is also the odd occasion where the amp will not power up and ends up oscillating.
Have tried slowing down the whole amp including Hawksford output stage but the effect persists.
Any ideas of what to try next. The fact that G-D caps made things worse has thrown me. It looks like power rails oscillations but I'm not sure.
Any hints would be massively appreciated.
Paul
Having problems with oscillation with Bob Cordell's Hawksford Error Corrected output stage. Using Cascoded drivers as per version in Bob's book. I like to use the BC3x7 devices. The output devices are 4 pairs of IRFP240/9240.
The oscillations start when I try to bias the output stage. Anything between 10mA and 100 mA per pair causes oscillation.
I have 100R gate stoppers and 100uF decoupling right at the drain pins. The cascoded drivers share the same rails as the MOSFETs. The decoupling caps have separate ground lines back to the PSU star point. The rest of the amplifier runs off separate power lines back to the bench PSUs. All this is built on stripboard so layout is massively compromised. If I try to add Gate to Drain caps (to one FET in particular) the oscillations get much much worse and the PSUs go from 28mA to 1.5 Amps draw where the current limit is set.
When I scope the rails there is about 500mV peak to peak oscillation visible in the 10Mhz. The gates are also oscillating at about 1V peak to peak. The ground lines back from the decoupling also show 500mV oscillation. Putting 1R+1u snubbers on the power rails doesn't help. Adding film caps didn't make any difference. The wires going back to the PSUs are very skinny (20 AWG).
There is also the odd occasion where the amp will not power up and ends up oscillating.
Have tried slowing down the whole amp including Hawksford output stage but the effect persists.
Any ideas of what to try next. The fact that G-D caps made things worse has thrown me. It looks like power rails oscillations but I'm not sure.
Any hints would be massively appreciated.
Paul
Layout is crucial for this type of circuit because of the high frequency operation within the loop. Have you tried the circuit with just one pair of mosfets? Paralleling mosfets can be problematic if the layout is not optimal. Where you attach the the small loop compensation cap that goes to gnd is important. A gnd track is not really gnd, but rather a small resistor + inductor leading back to gnd or the star gnd point, especially regarding high frequency signals. Not so critical with audio signals. Generally the driver stage has to be able to go beyond the power rail voltage in order to fully saturate the fet. This is usually done with either higher tier rails or using a bootstrap for the drivers. When you say you place a cap from gate to drain, you mean a small cap like 50pf or so? It may be better to use a zero instead of just a cap, like 100R + 50pf in series from gate to drain. Try to layout the circuit with a degree of symmetry and keep the high frequency connections as short as possible. Avoid wires and jumpers strung across the board in jumbled directions.
A Picture...
As requested, here's the schematic and .asc file. Uses mostly Cordell's models.
the schematic shows almost exactly what's built, less the decoupling caps. All component types and values are what is currently fitted.
Since the first post of this thread, have managed to answer a lot a questions by experimentation... And this schematic is the result of many hours work.
CBS,
Thank you for the reply.
Agree layout is critical. Have this, maybe mistaken, goal of getting it stable on strip board. Is this even possible using verticals? Still on a very steep learning curve and would like to learn more about controlling parasitics. I'm happy to let the performance of the amp drop if I can get control of the oscillations. Then when it comes to the PCB I can try and push the performance again.
Boosted rails will be added later.
The G-D cap was 33pF.
Paul
As requested, here's the schematic and .asc file. Uses mostly Cordell's models.
the schematic shows almost exactly what's built, less the decoupling caps. All component types and values are what is currently fitted.
Since the first post of this thread, have managed to answer a lot a questions by experimentation... And this schematic is the result of many hours work.
CBS,
Thank you for the reply.
Agree layout is critical. Have this, maybe mistaken, goal of getting it stable on strip board. Is this even possible using verticals? Still on a very steep learning curve and would like to learn more about controlling parasitics. I'm happy to let the performance of the amp drop if I can get control of the oscillations. Then when it comes to the PCB I can try and push the performance again.
Boosted rails will be added later.
The G-D cap was 33pF.
Paul
Attachments
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I think you may be trying to do too much at once. First off, I suggest you build the HEC stage first. If this is the first time you have built this circuit, you should simplify it, understand it and observe the operation, then move forward. Use one pair of outputs and one pair of drivers. Get the circuit stable first, and then try to expand on it. You may see RF oscillation bursts in the 10's of Mhz range at the peaks of the output signal under load, particularly reactive load. This is because the mosfet is ringing due to the much higher Gm of the mosfet at large currents. Increasing local mosfet compensation will prevent this and keep the circuit on the road to unconditional stability.
It is certainly doable to build this circuit on vero-board. Breadboard may give issues if the board is old and worn out.....like mine are.
I assume the inductors on the collectors are just to model lead inductance? It is important that the pins (and PCB traces) to the mosfet be as short as possible to minimize L.
There are a couple of things missing such as Vgs protection Zeners. It is important that these be as close to the device package as possible. RF oscillations can occur between the die and lead inductance resulting in an unsafe Vgs and mosfet destruction. In Bob's EC mosfet amp paper, he shows how a mosfet is really an oscillator and how to dampen the internal reactive components.
I sketched out a simpler version of the circuit (faster for me than on a PC) similar to one that I've built before. No higher tier voltage source required. I added reasonable current values for a bias. It is important that the gain of the error amplifier be unity. To this end, the Ix currents must be close to equal. You can calculate the resistor values using whatever power supply you intend. Bandwidth of the error amplifier should be as high as possible. Choosing faster error amp devices and/or a feedback pair (like Bob shows in his book) will yield better correction but it is important that the feedback/feedforward loop be compensated adequately by the pf caps on the collectors of the error devices and the pf cap from the emitters to gnd. Try a star on star type configuration. That is, connect the gnds of the decoupling caps together with that pf compensation cap from the emitters, and then use a single conductor to the power star gnd. Using 100nf film caps for additional high frequency decoupling will help with stability. The bootstrap essentially cascodes the driver stage. Also the driver stage can operate somewhere around +/-20V or so, greatly decreasing the Pd required for the driver transistors. I don't think Bob used a bootstrap, but it seems to work for me.
The error amplifier transistors must be in contact with the output stage heat sink to act as the Vgs multiplier. This may throw a kink in the layout but it does not hinder building a prototype version of this circuit. It may turn out that the circuit overcompensates and only one device is required for thermal compensation. You can experiment with that issue. You may find that using Zener diodes to set the first input stage bias will result in higher noise. Zeners are noisy and this makes them lousy voltage references in my opinion, at least for references that should be as quiet as possible.
It is certainly doable to build this circuit on vero-board. Breadboard may give issues if the board is old and worn out.....like mine are. I assume the inductors on the collectors are just to model lead inductance? It is important that the pins (and PCB traces) to the mosfet be as short as possible to minimize L.
There are a couple of things missing such as Vgs protection Zeners. It is important that these be as close to the device package as possible. RF oscillations can occur between the die and lead inductance resulting in an unsafe Vgs and mosfet destruction. In Bob's EC mosfet amp paper, he shows how a mosfet is really an oscillator and how to dampen the internal reactive components.
I sketched out a simpler version of the circuit (faster for me than on a PC
) similar to one that I've built before. No higher tier voltage source required. I added reasonable current values for a bias. It is important that the gain of the error amplifier be unity. To this end, the Ix currents must be close to equal. You can calculate the resistor values using whatever power supply you intend. Bandwidth of the error amplifier should be as high as possible. Choosing faster error amp devices and/or a feedback pair (like Bob shows in his book) will yield better correction but it is important that the feedback/feedforward loop be compensated adequately by the pf caps on the collectors of the error devices and the pf cap from the emitters to gnd. Try a star on star type configuration. That is, connect the gnds of the decoupling caps together with that pf compensation cap from the emitters, and then use a single conductor to the power star gnd. Using 100nf film caps for additional high frequency decoupling will help with stability. The bootstrap essentially cascodes the driver stage. Also the driver stage can operate somewhere around +/-20V or so, greatly decreasing the Pd required for the driver transistors. I don't think Bob used a bootstrap, but it seems to work for me.The error amplifier transistors must be in contact with the output stage heat sink to act as the Vgs multiplier. This may throw a kink in the layout but it does not hinder building a prototype version of this circuit. It may turn out that the circuit overcompensates and only one device is required for thermal compensation. You can experiment with that issue. You may find that using Zener diodes to set the first input stage bias will result in higher noise. Zeners are noisy and this makes them lousy voltage references in my opinion, at least for references that should be as quiet as possible.
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CBS,
Thank you for you comprehensive reply. It held the information I needed. It was balancing the Ix currents. Having done this the oscillation that was dependent on the biasing has gone. There is still a low level oscillation to deal with. This is only 10mV peak to peak. Tonight I shall add on the extra decoupling and gate to drain snubbers. Also will modify the grounding to star on star.
Maybe I have tried too much considering its not even been a year since I bought Bob Cordell's book and started this amplifier design "game"... Can't help it, its in my nature unfortunately. But I am prepared to fail and spend hours trying to work out what has gone wrong. It will not discourage me since as long as I'm learning I'm happy.
Yes, the inductors shown in the schematic are representing trace inductances.
Thank you for the hand drawn circuit. I think there is value in building it. Have pretty much reached critical mass as far as parts go. The only parts I don't have are small signal FETs. It will be interesting to compare your simpler more elegant design to my complex beast.
What do you suggest for alternatives to the zeners? simple resistor, vbe multiplier or something else?
Bonsai,
You were right. Very sound advice. Also, you were right (in the CFA Thread) about bypassing the VAS degeneration with small caps (pf). They do appear to add a zero.
All help much appreciated. Must get back to the experimentation
Paul
Thank you for you comprehensive reply. It held the information I needed. It was balancing the Ix currents. Having done this the oscillation that was dependent on the biasing has gone. There is still a low level oscillation to deal with. This is only 10mV peak to peak. Tonight I shall add on the extra decoupling and gate to drain snubbers. Also will modify the grounding to star on star.
Maybe I have tried too much considering its not even been a year since I bought Bob Cordell's book and started this amplifier design "game"... Can't help it, its in my nature unfortunately. But I am prepared to fail and spend hours trying to work out what has gone wrong. It will not discourage me since as long as I'm learning I'm happy.
Yes, the inductors shown in the schematic are representing trace inductances.
Thank you for the hand drawn circuit. I think there is value in building it. Have pretty much reached critical mass as far as parts go. The only parts I don't have are small signal FETs. It will be interesting to compare your simpler more elegant design to my complex beast.
What do you suggest for alternatives to the zeners? simple resistor, vbe multiplier or something else?
Bonsai,
You were right. Very sound advice. Also, you were right (in the CFA Thread) about bypassing the VAS degeneration with small caps (pf). They do appear to add a zero.
All help much appreciated. Must get back to the experimentation
Paul
The J-fet CCS reflected through the diamond buffer works pretty good if using a cascode or bootstrap. J-fets are generally limited in Vds. Choose and bias the J-fet at it's zero temperature coefficient Id so there is little fluctuation in bias voltage reference vs temp. A BJT CCS will work too, but J-fets are so simple.
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Update on the creation...
So here we are oscillation free (as far as I can tell on my slow scope). Firstly balancing the Ix currents sorted one problem out.
The following changes were made:
1) Grounding is now star on star.
2) Decoupling upgraded to electrolytic + Film. Thinking about adding 1R + 1u snubbers to damp possible ringing due to the paralleled caps.
3) Gate protection zeners added (Not shown on schematic).
4) Gate zobels added.
5) Added various gate stopper resistors in the HEC.
A lot of the changes were inspired by looking at the circuit CBS posted earlier. Not done the FET current sources yet as I have lack of small signal FETs.
After that I spent a long time scoping the circuit looking for the source of a low level 10mV peak to peak oscillation. After many hours it was traced back to one the switch mode PSUs. The star point ground at the PSUs was being heavily polluted. Changed to one of my many spares and the oscillation disappeared. Have a nagging thought though. Should the amp be able to handle heavily polluted supply rails with frequencies in the 10's MHz? Probably not as the ULGF of the main feedback loop is lower than the frequency of oscillation.
Then following the progress in getting some form of stability decided to up the performance a little...
1) Reduced C6 to 47pF. To speed up the HEC.
2) Reduced gate resistors to 39R.
3) Reduced feedback resistor to 470R while changing the feedback shunt resistor to maintain the same overall gain.
4) Tweaked cap + resistor across the feedback resistor to get good square waves.
Wondering what to do next? What is regarded as a high speed transistor for the HEC? Should I try to reduce gate stoppers further to take advantage of the distributed drivers?
So here we are oscillation free (as far as I can tell on my slow scope). Firstly balancing the Ix currents sorted one problem out.
The following changes were made:
1) Grounding is now star on star.
2) Decoupling upgraded to electrolytic + Film. Thinking about adding 1R + 1u snubbers to damp possible ringing due to the paralleled caps.
3) Gate protection zeners added (Not shown on schematic).
4) Gate zobels added.
5) Added various gate stopper resistors in the HEC.
A lot of the changes were inspired by looking at the circuit CBS posted earlier. Not done the FET current sources yet as I have lack of small signal FETs.
After that I spent a long time scoping the circuit looking for the source of a low level 10mV peak to peak oscillation. After many hours it was traced back to one the switch mode PSUs. The star point ground at the PSUs was being heavily polluted. Changed to one of my many spares and the oscillation disappeared.
Have a nagging thought though. Should the amp be able to handle heavily polluted supply rails with frequencies in the 10's MHz? Probably not as the ULGF of the main feedback loop is lower than the frequency of oscillation. Then following the progress in getting some form of stability decided to up the performance a little...
1) Reduced C6 to 47pF. To speed up the HEC.
2) Reduced gate resistors to 39R.
3) Reduced feedback resistor to 470R while changing the feedback shunt resistor to maintain the same overall gain.
4) Tweaked cap + resistor across the feedback resistor to get good square waves.
Wondering what to do next? What is regarded as a high speed transistor for the HEC? Should I try to reduce gate stoppers further to take advantage of the distributed drivers?
Attachments
It could be the lack of adequate decoupling. The amp only has 100uF + 100n per MOSFET and 2 x 100uF per rail of decoupling for the input stages.
The switch mode PSUs are quite powerful. They are designed for a max output of 150V @ 7.5A. They have continuously variable voltage output between 0 and 150 with continuously variable current limiting from ~10mA to 7.5A. Only drawing 60v @ 800mA. Wonder if they are struggling at these low levels.
Should I take the star point to Earth via a cap?
Been optimising (playing) a little this afternoon. Managed to get rid of the lead cap across the feedback resistor while maintaining good square waves without any peaking. Got decent stability margins too. Main loop PM = 81 Degrees and GM = 19dB (In sims) ULGF = 1.4 MHz.
The switch mode PSUs are quite powerful. They are designed for a max output of 150V @ 7.5A. They have continuously variable voltage output between 0 and 150 with continuously variable current limiting from ~10mA to 7.5A. Only drawing 60v @ 800mA. Wonder if they are struggling at these low levels.
Should I take the star point to Earth via a cap?
Been optimising (playing) a little this afternoon. Managed to get rid of the lead cap across the feedback resistor while maintaining good square waves without any peaking. Got decent stability margins too. Main loop PM = 81 Degrees and GM = 19dB (In sims) ULGF = 1.4 MHz.
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I wouldn't call that only.
Much more than many allow for.
It's not on the sch I looked at.
So here we are oscillation free (as far as I can tell on my slow scope). Firstly balancing the Ix currents sorted one problem out.
The following changes were made:
1) Grounding is now star on star.
2) Decoupling upgraded to electrolytic + Film. Thinking about adding 1R + 1u snubbers to damp possible ringing due to the paralleled caps.
3) Gate protection zeners added (Not shown on schematic).
4) Gate zobels added.
5) Added various gate stopper resistors in the HEC.
A lot of the changes were inspired by looking at the circuit CBS posted earlier. Not done the FET current sources yet as I have lack of small signal FETs.
After that I spent a long time scoping the circuit looking for the source of a low level 10mV peak to peak oscillation. After many hours it was traced back to one the switch mode PSUs. The star point ground at the PSUs was being heavily polluted. Changed to one of my many spares and the oscillation disappeared.
Then following the progress in getting some form of stability decided to up the performance a little...
1) Reduced C6 to 47pF. To speed up the HEC.
2) Reduced gate resistors to 39R.
3) Reduced feedback resistor to 470R while changing the feedback shunt resistor to maintain the same overall gain.
4) Tweaked cap + resistor across the feedback resistor to get good square waves.
Wondering what to do next? What is regarded as a high speed transistor for the HEC? Should I try to reduce gate stoppers further to take advantage of the distributed drivers?
Nice amp! Is this working amp?
You are making more complex amp then I do
. Could you put here .asc file, I would like to simulate it as it looks very interesting and innovative?BR Damir
Nice amp! Is this working amp?
You are making more complex amp then I do
BR Damir
Damir,
Thank you.
Yes, this is a working amp (Now soldered on strip board). It's not so much innovation on my part. Some ideas have come from Edmond's site and the CFA thread.
Once you look into this amp properly its not all that complex. Would say about the same level as you work at.
It would be good if you could simulate this. It may be a working amp but doesn't mean it hasn't got faults. Still very much a beginner in amplifier design.
The attached .asc is the latest proposed development. Will be implementing the DC Servo and changing the take off points for R47 and R48 later on. All other changes have been implemented.
Paul
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