SMSL SU-1 design idea

Like this. Pins at the other side of course.
 

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Checked my SU-1 for the mod... ouch,I forgot how tiny it is in there... I'm hesitating... + thinking again about the PLL power feed... why a PLL in a box that has an incoming asynchronous data stream (USB) and could make the output synchronous (i2s)? It just takes a SW buffer to have enough of data to feed the i2s + it should be in control of whats going on on the USB bus... no?

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My SU-1 as I ponder next mod...

Done:
OP-amp pow decoupling.
Osc pow decoupling.
vRef cap addition

and using LT3045 based 5V DAC power feed incl DC filtering.

considered output relay short-circuit but I happened to put the caps on op-amp first so could not access after that 🙂

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I forgot how tiny it is in there
I think this tweak has a reasonable place at already modded devices with external supply/etc, because this must be done at first step. Anyway you can try small sot23-5 0.9v for this rail

why a PLL in a box that has an incoming asynchronous data stream (USB) and could make the output synchronous (i2s)? It just takes a SW buffer to have enough of data to feed the i2s + it should be in control of whats going on on the USB bus... no?
I don't know why, but I hear big difference in any of XMOS where I did it. Manufacturers always give very simplified typical application schematics in such IC's (DAC IC's also...) and vaguely indicates that all power supply buses must be separated and so on.

My SU-1 as I ponder next mod...
1. External power supply
2. Separated good LDOs for left and right sides of 5V around AKM
3. External +- supply for output stage instead of PWM virtual negative source.
and many other things but it can be done only with using another case like in startpost in this topic
In some projects, a linear LDO (1117-1.8) was also used instead.
3.3V was always 1117-3.3

I think using LT3042 and similar LDOs in digital circuits is complete overkill.
I don't feel sorry for the money spent for hobby.
 
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OK, a little smaller. If someone has time please measure/analyze the function of the 10 pins. Maybe we can do something useful with them. Certainly with GND and possible 3.3V that would save the 2 input pins/wiring. It is now 12 x 17 mm and antenna-less. This regulator seems to have only 10 µV of noise and needs no extra parts for a quite low cost. I think this could be 10 Euro max. modification. Affordable, tiny, useful, exactly how I like it.

We don't want excess wiring, melt glue and air acrobatics constructions do we?
 

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thinking again about the PLL power feed... why a PLL in a box that has an incoming asynchronous data stream (USB) and could make the output synchronous (i2s)?
Typically in XMOS designs the PLL is used to generate the CPU core clock (several hundred megahertz) from a 13/24/48 MHz oscillator, and is not involved in I2S operation - a different clock frequency (MCLK) is used for this.

I don't feel sorry for the money spent for hobby.

Of course it is not forbidden to use LT3042 and similar here, but it makes no sense.
(Это ваши деньги, но это совершенно бессмысленно).

Alex.
 
That indeed makes no sense when it is not necessary.

Well if anyone has the time to measure/analyze the 10 pins and give that to me I will give the final gerbers to those interested. Especially a 3.3V and GND are of interest. The board can then be about just a 10 pin "plug" with only 1 output wire "+ clean 0.9V".
 
Please look at your device and how stuff is done. It is about removing a coil, clicking in the new plug, solder a thin wire from its output to the place where the coil was removed and be done with it. That is how I want to do it at least.

I need pin assignments and confirmation of pin to pin distance for the right pin header. My SU-1 is elsewhere now so I do stuff blind/from picture now.

This is how it looks when the plug is pushed in the pin header on the SU-1 PCB. Parts are on the other side. It is 11 x 14 mm now.
 

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Typically in XMOS designs the PLL is used to generate the CPU core clock (several hundred megahertz) from a 13/24/48 MHz oscillator, and is not involved in I2S operation - a different clock frequency (MCLK) is used for this.
Did your read this at all?

So you did that mod and found it improving the sound from your dac?

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If you are speaking to me: I take the information given by Anatolii_A seriously and I did look it up in the datasheet. I hadn't looked that deep into SU-1 as it is after all a very low cost budget DAC. Normally I find stuff out myself without needing someone pointing me to stuff but here I was not aware. One can not analyze every device passing through in minute detail. Simple.

The costs are low and the board is now 10.5 x 13 mm which is unobtrusively tiny. The version for a larger header is also still there. If someone gives the practical information I need I can finish the design and have boards made. So no I haven't tried (yet) if that was not obvious, yes I will have boards and yes I will try as it is now an easy job.
 
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I need pin assignments and confirmation of pin
This header is JTAG connector to XMOS. here is TDI/TCK/TDO/TMS/RST and 1,8V present when powered on, but seems to me that it is not power source voltage, but data line.
Also I find that second 1.8 voltage converter near 0.9 one is the same PWM. It's better to use good 5V on input of new regulator, it will be normal because PLL_AVDD current typ 5mA only.

So... Since I'm not going to give away my LT3042, I decided to show a simple example using sot23-5 regulator LDK130M10. It is not so good as TPS7A2009 but I have it. Any glue, just soldered to ground by ground pin and it also holded by soldered capacitors to ground around regulator.
1v_v2.jpg