The Well Tempered Master Clock - Building a low phase noise/jitter crystal oscillator

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Improper scope probing technique can create waveform aberrations that don't exist when the probe is not there. If someone claims a fast risetime clock waveform looks somehow bad, it would help to see a pic of the waveform and a description of the equipment and probing used to obtain the waveform. For example, long scope probe ground leads are one common cause of problems.
 
Improper scope probing technique can create waveform aberrations that don't exist when the probe is not there. If someone claims a fast risetime clock waveform looks somehow bad, it would help to see a pic of the waveform and a description of the equipment and probing used to obtain the waveform. For example, long scope probe ground leads are one common cause of problems.

The aberrations even exist with the BW and unknown Phase behavior or the DSO or Analog Scope & probe, while for a square wave may xx times higher linear phase is required... as for simple 10MHz with 500ps rise/fall a > 1Gs scope & probe is required :eek:
 
I made the measurements with a Picoscope 5444B. The output was connected with a coaxial cable and a 50 ohm termination. I don't want to commit myself to the topic of sound differences yet, as the time between the comparisons is several hours apart and I have also changed other things, but I will repeat the test again.
 

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Measuring the doublers

Thanks Andrea for your support. All boards are ready and working now.

Curious as always, I wondered if the doublers are very critical in their tuning, so what I did is measuring the 44.1 family (I did not do al four :rolleyes: ) with a sine wave generator as input to the doubler with the same pk-pk voltage as I measured from the output from the WTMC clock boards.

The output connected to my scope measuring the pk to pk output voltage (with 50 Ohm load)

I varied the frequency to generate a table/plot of frequency vs output voltage and looking for an "optimum" where the voltage is at its maximum

To be honest I thought it would be very critical, but as you see the doublers works perfectly on a somewhat broader frequency spectrum. I guess the figures and plot speak for it self.

Two Questions to Andrea, as you see the optimum is not 100% at the FS frequency:

1. Does that matter in any way?
2. If so, and performance could be improved, where to tune ?


:
 

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The problem is that the fine tuning of the frequency doublers would be very difficult because there are several capacitors in the filters which should be replaced with trimmer capacitors (at least 7 caps).

However the power loss does not affect the phase noise since it's very close to the theoretical increasing of 6dB for each multiplication.
Of course the noise floor increases a little in respect to the base oscillator because the frequency doublers use active devices.

So I think that the effort needed to get the the maximum amplitude at the output of the doublers does not worth.
 
Making some progress having finalized the clocks and doublers now and ready to move on with the "Clock Switch" project. Just finished the PCBs. Will test the Arduino code and signal functionality later today / this week :)

Light was a bit crappy for the pictures, so the PCBs looks worse than they actually are :D

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