Tips and suggestions on IRS2092 implementation?

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My definition of overkill is sizing a power supply much heavier than the voice coils can handle.

Finally 😀

...only down side is, that a simple trafo+rectifier+caps will show larger voltage sagging if designed to this point.
If optimized for size and weight a classd amp is powered best by a smps with stiff output voltage and high short term power capabilities. If a half bridge has to be supplied, then this SMPS should be able to source, but also sink currents at least in restricted manner. Can be sufficiently solved with a synchronous rectifier.

Last but not least the power handling capabilities of speakers are often not specified in a helpful way and I ended up in own measurements to detect the coil temp at certain AC loads by its DC resistance.

For DIY many people will prefer to simply oversize all power parts and make use of just a few percent. Then it doesnt matter if things are unmatched. Learning curve will come with the next party, which will highlight the weakest part of the chain.
 
officially, according to AES rules the manufacturer needs to state the temperature of the chassis when the power rating thermal equilibrium has been reached. this has always been the the hidden stuff. temperatures around 100degr C are no exception. the voice is coil already much hotter by then and has doubled its resistance.
for example Beyma was friendly to give me the values for a 12p1000Nd3.
at 900Wrms (4" voice coil) the chassis temp was 95degrC. the voice coil was 250degrC.
the standard says unit suspended in free Air.

that's why I prefer large voice coils. 64mm is a bit small for your 700W.
 
Finally 😀

...only down side is, that a simple trafo+rectifier+caps will show larger voltage sagging if designed to this point.
If optimized for size and weight a classd amp is powered best by a smps with stiff output voltage and high short term power capabilities. If a half bridge has to be supplied, then this SMPS should be able to source, but also sink currents at least in restricted manner. Can be sufficiently solved with a synchronous rectifier.

I don't really have weight/size (nor cost) restrictions, I do think (in my limited experience at least) that a SMPS leaves a bit to be desired still in terms of reliability and ruggedness.

I've been using SMPSs for linear amplifiers as well as class-D (Hypex) and unfortunately, due to the crest factor mostly, SMPSs either need to be designed for audio, or be able to offer substantially higher peak power than your average run-of-the-mill SMPS.

In terms of reliability I've had two SMPSs die on me in the last year which have seen just over three years of use. One has dried out secondary caps which need to be replaced, which raised the HF ripple to a point the linear amplifier would oscillate. The other has a defective primary section.

I also have many linear and class-D amplifiers with a simple transformer+bridge+caps power supply that are running reliably even after 10-years of use. Hence my personal preference would be to keep it simple and stick with the transformer+bridge+caps solution. Obviously your mileage may vary and I'm sure that for PA use such a solution is prohibitively large and heavy.
 
... that's why I prefer large voice coils. 64mm is a bit small for your 700W.

A large part of the allowed maximum has got to do with the cooling of the voice coil. If there's no cooling offered in terms of venting air from the cone through the spider/airgap then temperatures will rise quickly and thus reliability might be an issue.

Please keep in mind that this design is intended for home use, with two of these drivers running in parallel. The acoustical output at >500W will be upwards of 120dB which is far from typical listening levels. I.e. this is a scenario that might never occur in practice, and if so, certainly not for prolonged periods of time.
 
I spent some time over lunch drafting a first schematic, however there are some inconsistencies between the IRS2092 datasheet (http://www.irf.com/product-info/datasheets/data/irs2092.pdf), the AN-1138 application note for the IRS2092 (http://www.irf.com/technical-info/appnotes/an-1138.pdf) and the schematics of the various demo boards. For example IRAUDAMP9 (http://www.irf.com/technical-info/refdesigns/iraudamp9.pdf).

Most of these inconsistencies have to do with the MOSFET gate drive configuration. For example the typical application circuit in the AN-1138 application note (page 2) shows the CSH pin (16) connected to the positive rail via a BAV19 diode and the VB pin (15) connected to the positive rail with a resistor as shown below and a resistor between the CSH (16) and HO (14) pins:

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However the IRS2092 datasheet (page 1) shows a different configuration, with the CSH pin (16) connected to the positive rail with a resistor AND a diode and two resistors between the HO pin (14) and the CSH pin (16) as shown below:

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The IRAUDAMP9 demo board schematic then shows something which is different again. The HO pin (14) is not connected to the positive rail in any way and the VB pin (15) and CSH pin (16) are now connected through two resistors (R25, R43).

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Hence we now have three variations of how to wire the IRS2092 into a schematic and the datasheet and the application note, nor the demo board documentation lists any reason as to why these pins are wired differently.

Is this application specific? A way to prevent current sharing between pins perhaps? Are they all correct?
 
And here's the schematic I drafted that has the following specifics:

1) IRS2092 gain set to 5x to improve S/N ratio
2) Opamp front-end with gain set to 4x
3) Overall gain is 26dB (20x)
4) MOSFET deadtime setting with resistor (R24) and flyback diode (D26) and drain to rail/output (R26)
5) Resistor+zener+78xx/79xx for opamp power supply
6) Snubbers across each MOSFET (R28, C25 and R29, C26)

Most of the resistor values around the IRS2092 need to be calculated still as per the application note, hence these values are missing from the schematic.

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For some reason the images in my post #47 have stopped showing, here's the images again in the order they should appear.

AN-1138 - application note schematic

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IRS2092 datasheet - principal schematic
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IRAUDAMP9 demo board - schematic detail
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I spent some time over lunch drafting a first schematic, however there are some inconsistencies between the IRS2092 datasheet (http://www.irf.com/product-info/datasheets/data/irs2092.pdf), the AN-1138 application note for the IRS2092 (http://www.irf.com/technical-info/appnotes/an-1138.pdf) and the schematics of the various demo boards. For example IRAUDAMP9 (http://www.irf.com/technical-info/refdesigns/iraudamp9.pdf).

Most of these inconsistencies have to do with the MOSFET gate drive configuration. For example the typical application circuit in the AN-1138 application note (page 2) shows the CSH pin (16) connected to the positive rail via a BAV19 diode and the VB pin (15) connected to the positive rail with a resistor as shown below and a resistor between the CSH (16) and HO (14) pins:

However the IRS2092 datasheet (page 1) shows a different configuration, with the CSH pin (16) connected to the positive rail with a resistor AND a diode and two resistors between the HO pin (14) and the CSH pin (16) as shown below:

The IRAUDAMP9 demo board schematic then shows something which is different again. The HO pin (14) is not connected to the positive rail in any way and the VB pin (15) and CSH pin (16) are now connected through two resistors (R25, R43).

Hence we now have three variations of how to wire the IRS2092 into a schematic and the datasheet and the application note, nor the demo board documentation lists any reason as to why these pins are wired differently.

Is this application specific? A way to prevent current sharing between pins perhaps? Are they all correct?


CSH is measuring Vds voltage when High side is on.
In figure attached, D1 is reverse blocking diode which blocks high voltages into CSH pin when high side is off.

It is forward biased through R1. Since HO == VB when high side is on, R1 can be attached to either HO or VB.

CSH is internally fixed at 1.2V, so R2 and R3 voltage divider is used to program the high side OCP into higher threshold.

Resistor connected to pos rail and VB is required for bootstrap capacitor charging at startup.

So all schem are correct.
1. In AN1138 schem, High side OCP trip is being set at default VDS = 1.2V. CSH monitors I * Rdson. 33k resistor is startup bootstrap charger.
2. In IRS2092 Datasheet, a voltage divider is added at CSH, which will set the OCP threshold higher depending on the resistor values. Bootstrap resistor is missing.
3. IRAUDAMP9 schem is the same as #2. Also has resistor R26 which slows down charging of bootstrap cap. R40 is startup bootstrap charger.
 

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The driver heat grows almost with the square of the driver supply voltage.


4227 is a tough one, nevertheless a single pair of 4227 will have a life on the edge with this and survive just because fs drops towards larger signals.
Detailed measurements and analysis of worst case switching losses and calculation of die temperature would tell you that you are brave man. 🙂
Please keep us tuned about your reliability experiences of this set up.
Can't provide detailed measurements 😱

At idle condition 270kHz, left for more than an hour, chassis closed,
IRS2092 with DIP heatsink stays at 48deg C, Inductor around 42deg. What bothers me is the bootstrap cap, I'm using 47u 63V low leakage, it is hotter than IRS2092. Though it is rated at 105deg at 2000hr.

Zobel resistor and inductor heats up when operating frequency is lower than 300khz.

4227 is as hot as TIP31C VCC regulator. Heatsink is 40 deg celsius.

At 55V DC rails, module power consumption is only 7W 🙂
 

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@jlester87,

Thanks for the insightful reply. I hadn't thought about that yet, but after looking over the application note in greater detail once more it is indeed as you described. I had not gotten around to calculating these resistor values yet, hence I didn't read that part of the datasheet in enough detail.
 
I was a bit of a slow afternoon at work, so I figured I'd throw together a quick simulation of the schematic I posted earlier. This is just to look at loop gain etc. as the switching behavior or the MOSFETs etc. are obviously not modeled.

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In terms of reliability I've had two SMPSs die on me in the last year which have seen just over three years of use. One has dried out secondary caps which need to be replaced, which raised the HF ripple to a point the linear amplifier would oscillate. The other has a defective primary section.

True. The old monster magnetics are hard to beat in terms of reliability.
Even worse, most SMPS designs in the market do not even target reliability, but cost cut. Similar thing with ClassD amps. :apathic:
 
Heavy drivers, so they are not the limiting factor.

The problem at these low frequencies and with Linkwitz transform is going to be bus pumping. There is the technical approach, a full bridge that can work with much less capacitance, or the brute force approach, a half bridge with a lot of capacitance, I did a quick simulation and 40mF per rail (2x) gives something like 10% p-p rail ripple at 40V rms output on 2 ohm (800W, +/-70V). A full bridge for that power could do with just 20mF single 70V rail. Not counting sagging in both cases.

IRS2092 is good as an starting point, but the simplicity of its built-in OTA is not suitable for full bridge, so simplicity is traded for increased cost of capacitors. This is the point I was trying to make previously, going below a certain complexity threshold always increases cost somewhere else. My start point for audio class D was a breadboard with a IR2011, 2x 100V fets, +/- rails from 30V max. bench supply and a LM311 comparator. I still have it somewhere. Good enough to be listened and did not self destruct. Next attempt was already 2 channel, using daughter-board for modulators, and with SMD.

In my opinion, the simplest approach to start with: IRS2092 (noise requirements are relaxed for LF), NPN/PNP buf, 2x IRFB4227, not so high VA transformer, +/-80V (idle) to relax sag requirements, and old-school cap bank.

Some details from the output stage drive circuits you posted:

- Image from post 48 is missing, I was not able to see the schematic.

- The pull-up resistor that biases high side current limiting (10k in some sch) is shown connected to VB in some examples and to HO in others. Connection to HO is more efficient and has no drawbacks. Connection to VB requires lower value (VB-VS) charge resistor(s). For the current limiting thresholds I recommend leaving room in PCB for dividers, 2 resistors, although one of the resistors may not be needed.

- Using a single resistor to charge (VB-VS) implies that a speaker load must be connected, or the amplifier may not start. Turn-on pop is increased. My approach is to add a second resistor from VS to VCC, this allows starting with no load.


Choco:

In SMPS, like in any other challenging field, there is imitation and innovation. Low reliability always comes from poor or outdated imitation. In the innovative front there is always high reliability. The brute force approach results in high use of natural resources for leisure applications, or even worse, the proliferation of cults to natural resource waste. So the brute force approach is unreliable, not in the sense of losing function with time, but in the sense of making the whole world in which we live unreliable!! haha
 
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Housekeeping:
The use of half bridge is going to require rail monitoring (Vmin and Vmax) and a protective mute cycle for maximum reliability. I would also include DC protection with output relay, and one NTC in the heatsink and another in the transformer, both driving the mute circuit in case of oveheat. Another interesting gadget would be a circuit detecting CSD fall pulses (current limiting) and integrating these pulses to another capacitor to measure the density of current limiting, intended to mute the amplifier if current limiting extends for more than a few ms, but allow brief current limiting without shutdown.
 
I found bus pumping was only an issue when testing the amp wit h signal generator with low frequencies.
With normal music I had no problems.

I did have a problem using large capacitors on the power rails, on power down the speaker would have a loud siren type noise for a few seconds then end with a huge thump. IR said it was slow discharge of power supply on power off and I needed to hold 2092 in reset when VCC became too low. I did it with an 8 pin PIC and an opto-isolator. It was fine after that.
 
Of course these gate drive ICs are all intended to be driven from some kind of logic that, at least, checks the rails. No class D loop will behave at very low rails because the amplitude of carrier at comparator inputs decreases linearly with rails, to the point where parasitics take over. The simplest possible logic is to derive the VAA and VSS rails in such a way that this section of the IC enters UVLO before the amplifier starts misbehaving as rails drop at power off (ressitors from HV rails, small value capacitors, maybe draining resistors too). In my current project there is a 100 pin 100Mhz PIC32 doing complete supervision of 4 half bridges, including too short and too long PWM pulses, adjustable clip limiter, also limiting in case of excessive supply pumping and other incidences, etc. MCUs are useful for implementing full-reliability no-safety-hole housekeeping without lots of parts.
 
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I did have a problem using large capacitors on the power rails, on power down the speaker would have a loud siren type noise for a few seconds then end with a huge thump. IR said it was slow discharge of power supply on power off and I needed to hold 2092 in reset when VCC became too low. I did it with an 8 pin PIC and an opto-isolator. It was fine after that.

For DIY home use, speaker protect with fast relay turn off that disconnects the output at power off is sufficient.

@Eva
What can you suggest to reduce heating at bootstrap capacitor? I am using a relatively large diameter electro cap for it to distribute heat. Thanks!
 
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