Well... my instincts were wrong (not the first time). The issue is a layout error.
This new version has a updated footprint for the JFETs that supports TO-71 only. This gave a bit more creepage clearance on some of the trace and pad spacing. However, despite reviewing this multiple time, it looks like a mixed up the pinout. It should be G-D-S and I have it as S-D-G. And, its not just a silkscreen error. The traces are in fact mixed up. I think I misinterpreted the datasheet as a bottom view, despite the labeling as a topside view.
I need to think about this to see if I can twist the pins with some heat shrink wrap on them to get a correct mounting and verify this is the only issue. Hopefully it didn't fry $20 in JFETs
I'm glad I choose to complete a test build before releasing the boards to other builders.
I'll need to fix the layout and order a new batch of test boards. It will allow me to correct some other minor issues I encountered.
This new version has a updated footprint for the JFETs that supports TO-71 only. This gave a bit more creepage clearance on some of the trace and pad spacing. However, despite reviewing this multiple time, it looks like a mixed up the pinout. It should be G-D-S and I have it as S-D-G. And, its not just a silkscreen error. The traces are in fact mixed up. I think I misinterpreted the datasheet as a bottom view, despite the labeling as a topside view.
I need to think about this to see if I can twist the pins with some heat shrink wrap on them to get a correct mounting and verify this is the only issue. Hopefully it didn't fry $20 in JFETs
I'm glad I choose to complete a test build before releasing the boards to other builders.
I'll need to fix the layout and order a new batch of test boards. It will allow me to correct some other minor issues I encountered.
- The pin hole size for R18 was a bit tight. I'll enlarge from 0.9mm to 1.0mm (or maybe 1.1mm)
- The mounting holes are a bit tight. They don't have enough slop for manually tapped holes that aren't always perfect. I'll enlarge from 3.4mm to 3.6mm
- I might increase the footprint pitch of R19 from 20mm to 25mm. The boards do have room for this.
- The 1/4W resistors are a mix of 10mm and 12mm pitch. I might try to make them all 12mm pitch, as this will make construction simpler.
My tips for the first amplifier tests.
Normally, the first time, I join the output point of the amplifier to the VAS and remove the power mosfets, then I place a 1K 5W resistor (as dummy load). And so I make the first measurements, I adjust the DC voltage between the gates of the mosfets to "0v" and everything should work like a normal amplifier.
Next I remove the jumper from the output to the VAS and place the power mosfets, and then I adjust the bias. I always use power supplies with an adjustable current limit of 100mA per rail. Failing that, if you don't have one, use 500mA fuses on the rails, buy plenty. cheer up!!!
It is quite normal that it does not work the first time, small errors always happen. The important thing is that important or expensive parts do not burn.
Normally, the first time, I join the output point of the amplifier to the VAS and remove the power mosfets, then I place a 1K 5W resistor (as dummy load). And so I make the first measurements, I adjust the DC voltage between the gates of the mosfets to "0v" and everything should work like a normal amplifier.
Next I remove the jumper from the output to the VAS and place the power mosfets, and then I adjust the bias. I always use power supplies with an adjustable current limit of 100mA per rail. Failing that, if you don't have one, use 500mA fuses on the rails, buy plenty. cheer up!!!
It is quite normal that it does not work the first time, small errors always happen. The important thing is that important or expensive parts do not burn.
Hi Adiaz,
I used 500mA fuses for the first power on test. Troubleshooting gets a bit trickier with new boards, as it's not always clear if a problem is a construction error or a problem with the layout. Unfortunately, it was the layout this time. But, that happens with new designs. Hopefully I can twist the leads and at least determine if this is the only issue.
But, it'll have to wait. Time to take the youngsters Christmas shopping for gifts for mom.
I used 500mA fuses for the first power on test. Troubleshooting gets a bit trickier with new boards, as it's not always clear if a problem is a construction error or a problem with the layout. Unfortunately, it was the layout this time. But, that happens with new designs. Hopefully I can twist the leads and at least determine if this is the only issue.
But, it'll have to wait. Time to take the youngsters Christmas shopping for gifts for mom.
It is a bummer when you get jazzed up for a verification build and then it gets derailed, but these things happen. I greatly appreciate you putting the time and effort in before they go out in the wild.
Just a couple of thoughts... If you have any questions or doubts about slightly increasing component hole size or part space just do it. Better to err on the bigger side than too small. Not every builder will use the same part brand/model and lead thickness varies, especially resistors and capacitors.
Now, go battle some crowds and take the little ones shopping!!
Merry Christmas Brian and ALL!!
Just a couple of thoughts... If you have any questions or doubts about slightly increasing component hole size or part space just do it. Better to err on the bigger side than too small. Not every builder will use the same part brand/model and lead thickness varies, especially resistors and capacitors.
Now, go battle some crowds and take the little ones shopping!!
Merry Christmas Brian and ALL!!
I was able to twist the JFET leads and power it back up. DC offset is now under 20mV without trimming and I can set the OPS bias. However, the VAS current is not where is should be. I'm getting 6 mA when it should be around 20mA.
I'm wondering if the VAS devices got damaged. I'm going to try replacing the VAS transistors tomorrow.
I'm wondering if the VAS devices got damaged. I'm going to try replacing the VAS transistors tomorrow.
A quick update:
I don't have any new progress to report. Work and life at home have kept me away from the bench. Hoping to get back to it this weekend or next with some actual progress to report.
I don't have any new progress to report. Work and life at home have kept me away from the bench. Hoping to get back to it this weekend or next with some actual progress to report.
Lineup and Brian: Could any of you please comment on the last postings in the original thread? It is about thermal instability when using HEXFETs in the ciruit.
Thanks!
Thanks!