these values are given by deltaVgs=deltaVbias, and vbias for the N part around 5v?
also, r3t/r4t source resistors must be calculated as per Fran recommendation?
Thanks
These values are very different compared to the BOM supplied values, how are they calculated?
There is a calculation included in Fran's build guide to determine the value of R3t and R4t.
Folded Cascode CEN IV is my circuit. The original BoM was made by me.
It was based on the assumption that the Vgs of both NMOS and PMOS were close to identical, as in my own proto.
The purpose of those resistors are to set the drain of the JFETs at approximately 1/2 rail voltage.
Since this particular batch of MOSFETs have rather different Vgs values (but still in spec.), the potential dividers have to be adjusted to suit.
And as I intend to use standard resistor values, the impedance have also been (roughly) halved.
Fran's calculation is intended for fine triming only.
You don't have to do what I say.
By all means, use the original values and see what you get at the drain of K170/J74.
Cheers,
Patrick
It was based on the assumption that the Vgs of both NMOS and PMOS were close to identical, as in my own proto.
The purpose of those resistors are to set the drain of the JFETs at approximately 1/2 rail voltage.
Since this particular batch of MOSFETs have rather different Vgs values (but still in spec.), the potential dividers have to be adjusted to suit.
And as I intend to use standard resistor values, the impedance have also been (roughly) halved.
Fran's calculation is intended for fine triming only.
You don't have to do what I say.
By all means, use the original values and see what you get at the drain of K170/J74.
Cheers,
Patrick
Last edited:
I do not understand why it is so difficult just to do as I adviced.
For the batch of MOSFETs measured by Fran, the NMOS Vgs varies from 2.16 to 2.42V.
The PMOS Vgs varies from 1.76 to 1.89V.
So variations between NMOS is ~0.25V, and between PMOS ~0.14V.
Average difference between PMOS and NMOS is, on the other hand, ~0.5V,
i.e. much larger than those between NMOS and between PMOS.
Fran has sorted the sets such that you do get P & N difference close to the 0.5V value.
This difference is then taken care of by the R1~R4 resistor values I calculated for you.
The small remaining difference should be less than 0.2V.
And this will then be taken care of by R3t, R4t.
Adding a large value of R3t-R4t will ruin the symmetry of the circuit.
As said, you don't have to listen to me. Do what you think is best for you.
Patrick
For the batch of MOSFETs measured by Fran, the NMOS Vgs varies from 2.16 to 2.42V.
The PMOS Vgs varies from 1.76 to 1.89V.
So variations between NMOS is ~0.25V, and between PMOS ~0.14V.
Average difference between PMOS and NMOS is, on the other hand, ~0.5V,
i.e. much larger than those between NMOS and between PMOS.
Fran has sorted the sets such that you do get P & N difference close to the 0.5V value.
This difference is then taken care of by the R1~R4 resistor values I calculated for you.
The small remaining difference should be less than 0.2V.
And this will then be taken care of by R3t, R4t.
Adding a large value of R3t-R4t will ruin the symmetry of the circuit.
As said, you don't have to listen to me. Do what you think is best for you.
Patrick
Jim, that is roughly where I was out at. Having built before any adjusted values were revealed and using the instructions in BOM, I can say that I was able to achieve stable offset at less than 5mV and it sounds great. At some point I may redo some things and try these new values, but it’s hard (for me) to justify at this point.
You missed the whole point.
It is not about whether you can set output DC offset or not.
It is about even harmonic cancellation in the push-pull circuit.
Pulling the circuit out of symmetry will create unequal current sharing between the upper and lower parts of the circuit.
The result is increased 2nd harmonics.
But maybe some people prefer to have 2nd harmonics afterall.
I shall change the trimming with trimpots in any later GBs (if any at all).
Then no more discussion, even though I hate to use trimpots in my own build.
Cheers,
Patrick
It is not about whether you can set output DC offset or not.
It is about even harmonic cancellation in the push-pull circuit.
Pulling the circuit out of symmetry will create unequal current sharing between the upper and lower parts of the circuit.
The result is increased 2nd harmonics.
But maybe some people prefer to have 2nd harmonics afterall.
I shall change the trimming with trimpots in any later GBs (if any at all).
Then no more discussion, even though I hate to use trimpots in my own build.
Cheers,
Patrick