Hello everyone, I am currently implementing UAC2 on STM32F446RE. Now it supports up to PCM 352.8k and DSD64(DoP). Please give it a shot if you are interested.
Source code
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Source code
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Based on the reference manual I'm not sure if master and slave data (in this case DSDL and DSDR) is synchronized so there may be slight timing offset between DSDL and DSDR. That probably does not matter. But since SAI provides synchronization and I2S has no real benefits why not just use SAI.IIUC the two I2S interfaces have their clock pins connected, and I2S3 is master while I2S1 is slave. The two interfaces should run synchronously if started closely to each other, IMO. Or can there be some race condition?
Hi bohrok2610,Well done!
Couple of comments from quick glance:
- Instead of PLL it would be better to use external clocks for MCK. STM32F466 allows this through I2S_CKIN (PC9).
- SAI would probably be more future-proof than I2S as with F7 & H7 SAI is much more evolved and feature-rich than I2S.
- The limits for async feedback at 44k1 (and multiples) are not symmetric as is the case with 48k (and multiples). This is not a huge issues as host just discards feedback that is not within limits.
- I assume this is intended to be similar to Amanero. Still I would add isolators for all output signals.
Much lower jitter is possible with external clocks but this of course depends on the clocks. Also fs frequency would be exact without error.Maybe for lower clock jitter?
LQFP100 has SAI2A&B available.The first comes to my mind is indeed SAI. Unfortunately, on 64-pin devices it collides with ULPI signals.
Currently two. Theoretically the USB code can do more, but it would require external CPLD to handle channel splitting.Cool project! How many channels can this solution handle?
The clock is actually exact. 44.1k is 147/160 of 48k. I2S_SetFreq() in usbd_audio_if.c handles this case.Much lower jitter is possible with external clocks but this of course depends on the clocks. Also fs frequency would be exact without error.
Currently not. As it will require composite device support, which the library does not provide.slerpxcq, very interesting project, do you have plans to add an ADC option?
I2S2 is still available. All 3 I2S's do not collide with ULPI.The 64-pin chip probably does not have available I2S or SAI interface. But suitable FW exists already:
https://www.diyaudio.com/community/threads/uac2-i2s-input-on-stm32f723e-disco.393702/
This is easily achievable as I2S_CKIN and RCC_MCO2, which is used as MCK output, are the same pin.Ok, I did not notice that you are using audio frequency clock as HSE. With DS DACs external MCK via I2S_CKIN would probably work better as you can use the same MCK at DAC and I2S stream is synchronized. Otherwise reclocking of I2S may be needed.
I2S does not have synchronization between interfaces so I2S input & output would be asynchronous (i.e. 2x half duplex). Synchronization with I2S could be done with external MCK assuming same clock is used in both DAC & ADC.I2S2 is still available.