A Lateral MOSFET Power Amplifier Design Version 1.1

Your speaker return must go to masse and the HQG goes to your power supply 0V. It might be easier to move sortie to the right so it’s located right next to masse - easier for wiring 😊
So return with only one connector as they have two screws each.

Now, this topology is looking much like a ground plane than a star distribution for me :) Since the beginning of this project I had a star topology in mind and I remember having read that a ground plane is not recommended for an amplifier.
We must admit here that they are different opinions after all lol
Thanks again for all your help Bonsai!

I'll keep this thread updated once finished...
 
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Non problem 👍

It’s not really a ground plane - the ground, supply and output rails are just grouped to minimise EM radiation while for the input small signal ground and feedback paths, it’s grouped together to minimise susceptibility. The ground connections at HQG are definitely star ground to make sure there is no common impedance coupling.
 
So, here is the latest version. I tried to keep in mind that all powers rails and NFB traces should have a ground surface over them on the components side. I also putted the two TO-220 transistors of the VAS back to back with their own heat-sink. I am surprised how space available is still there, even after having shorter the length of the PCB. I also minimized the Power of resistors R503/504 and R603/604 to 0.250W. I kept some spare space for the coil L1 knowing that the number of required turns an diameter for the original 3uH is a bit bigger and longer than the 3D model.

I kept the R4 resistor ground trace to the Speakers connector isolated with it's own trace on layer Cu2. I also tried to minimise the components ground surface as much as possible while prioritizing the cover of sensible traces under it on the others layers.

All the Input and VAS ground are isolated from the components ground surface, the latest reserved for +/-rails ground. Here some captures in the goal to well visualize all the details explained above.

Here are the +49 VDC traces first, followed by the same picture with the ground surface of the components layer. The only one trace on another layer is highlighted on the Cu2 layer in the third picture:

Capture d’écran du 2024-05-31 16-50-42.png


Capture d’écran du 2024-05-31 16-51-13.png

Capture d’écran du 2024-05-31 16-51-34.png



Here are the -49 VDC traces first, followed by the same picture with the ground surface of the components layer:

Capture d’écran du 2024-05-31 16-52-18.png

Capture d’écran du 2024-05-31 16-52-45.png


Then the Cu1 internal layer, followed by the same image with the Components layer surface that cover the NFB traces:

Capture d’écran du 2024-05-31 16-53-23.png


Capture d’écran du 2024-05-31 16-53-43.png


Idem for the Cu2 internal layer:

Capture d’écran du 2024-05-31 16-54-04.png


Capture d’écran du 2024-05-31 16-54-28.png


And finally all four layers showed:

Capture d’écran du 2024-05-31 16-54-51.png


Same as above but from the Gerber viewer:

Capture d’écran du 2024-05-31 16-58-03.png



Finally some 3D pictures of the final board:

Figure 14.17.Rev1.1.kicad_pro.png


Figure 14.17.Rev1.1.kicad_pro_ÉlĂ©vation.png


Figure 14.17.Rev1.1.kicad_pro_Profil.png


Figure 14.17.Rev1.1.kicad_pro_ISO.png
 
If this is an initial design, I may be tempted to make the board out of multiple lower cost PCBs (smaller size that fit into their cheap protoboard size) split - powersupply, driver, power stage etc. That way you can adjust as you go along and typically you get 5 boards or so for each panel design (although protoboards typically are restricted in copper thickness).
The reason is the larger boards typically are more expensive and one mistake in a 4 layer board can result in a completely unusable board.

This technique doesn't stop you from making a panel that is a number of designs on one - such as a driver section but to use up the board space, add some regulator designs etc that are separate from the copper pour etc and then cut them to divide them using a Dremel or tile hacksaw. Just remember to have enough thickness for the blade and some more for human accuracy between the designs.
I do this for my PCB designs and you build up an inventory of bits you know you will need for future projects.

Also note that you will probably get charged more for internal via or micro vias. I will typically use through visa for the most part.

Last point - careful of the tolerances of manufactured parts. C506 seems to be up against the large cap next to it. Large caps can also 'sing' under heavy load. I had that with my amp on the dummy load - you could hear the test tune due to the caps singing. You'll need to be able to glue them down too (or silicone but silicone can turn acidic over time). So any splurge at the base will cover close components too.
 
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The splurge comment is that the silicon/glue can then act like a thermal insulator, lowering the thermal rating of that part (sorry if that reasoning wan't clear). So just consider that - I've seen 5W resistors glued to PCBs and splurge covering components that really need cooling (adds noise and can increases failures).
 
If this is an initial design
Also note that you will probably get charged more for internal via or micro vias. I will typically use through visa for the most part.
This is not a first design. I have already builted two working PCBs based on the exact same schematic. The raison I redo the PCB is because my lack of experience in Amplifier routing have made me make the mistake of routing long separate traces for the +/-rails power supply, that have created ground loop. The amplifier is already builted into it's 3U Modushop case and it was already pleasant to listen, except for a tiny tiny little hum on one channel. That hum as been the whole starting point of this new thread.

I have no micro VIA. I made a simulation of the cost and yes it is more than the double for the same size two layers one. But if you have a closer look at the traces layers above, unless you make the design on separate boards as you proposed for each section (IPS, VAS, OPS), it is impossible to make it with only two layers. I tried more then fifteen time lol.
 
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Last point - careful of the tolerances of manufactured parts. C506 seems to be up against the large cap next to it. Large caps can also 'sing' under heavy load. I had that with my amp on the dummy load - you could hear the test tune due to the caps singing. You'll need to be able to glue them down too (or silicone but silicone can turn acidic over time). So any splurge at the base will cover close components too.
Thanks! But I already have the parts in stock and double verify their size. But still, you made a good point gluing them...
 
With the goal to include TMC on my circuit, I added two capacitors and two resistors to the board. This make me realized one big mistake I did. The decoupling capacitors C303/C403 were wrongly connected to the audio path ground. I corrected them and stretched the ground surface over them. And I rerouted the ground traces.

Capture d’écran du 2024-06-03 07-53-55.png


New ground traces highlighted.

Capture d’écran du 2024-06-03 07-54-41.png


I also rerouted the NFB traces in order to have two traces of them on different layers; one above the other. I also rerouted the L1 coil to the MOSFET more symmetrical, for the minimum traces resistance possible.

Capture d’écran du 2024-06-03 07-57-30.png


Capture d’écran du 2024-06-03 07-58-00.png


Capture d’écran du 2024-06-03 07-58-23.png


Now, back into LTSpice for simulation to search the best TMC capacitor values, I had the best results when I keep the C301/401 lower than the C302/402. From all the books I have, it is written that the C2 (here C302/402) should be much greater than C1 (here C301/401). In my case, in the goal to keep the 0dB Frequency pole between 1MHz and 2MHz, I MUST keep C1 (C301/401) close to it's original Miller Compensation value of 10pF. Then I obtain better THD at 1kHz and 20kHz if I lowered the C2 value (C302/402). Here is a table showing all the results. The color code formula compare all the values in the same column and report the best (Green) and the Worst (Red) case. I get the best result with C1 (C301/401) at 10pF and C2 (C302/402) at 5pF. The resulting sum would get 3.3pF, much lower than the 10pF original Miller value!

Capture d’écran du 2024-06-03 18-01-29.png
 

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Hello,

After several simulations in LTSpice and with a first PCB version without electrical errors, I am confident to proceed with the fabrication of this new PCB design. This circuit offers me the possibility of preserving Cdom according to the original design and experimenting with a TMC design by adjusting capacitor and resistor values in practice. However, given the double cost of manufacturing a 4-layer circuit, I obviously want to do my utmost to ensure the success of this design. This is where I appeal to all members experienced in audio PCB design to let me know if you have any doubts about this design. If you believe that certain traces are unsuitable for an audio amplifier, I'm always open to your suggestions and/or advice.

In drawing up my parts list, I had to replace the diameters of the C501, 701 and 801 capacitors with smaller ones, as the previous capacitors were no longer available from Mouser. I'm attaching a final capture of all the layers for reference, but the traces have been modified only very slightly to adopt the new pin spacing.

It goes without saying that I take full responsibility for any failure of this circuit in its final form.

@Bonsai, at the risk of repeating myself, I'd like to thank you in particular for all your previous comments! Following all your advice, this circuit looks nothing like its first version and I'm very excited to assemble it and see the final result.

Thanks in advance to everyone and thanks to all those who have already contributed with their previous comments.

Capture d’écran du 2024-06-06 08-19-57.png
 
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