That makes sense in terms of A minimal signal chain. Your preamp / amplifier may have a capacitor somewhere in the signal chain. DC on volume controls is usually not a good idea. There are some balanced input stages that could tolerate +2.7 volts dc common mode on the inputs but you still need to control volume somehow. An input transformer that could tolerate a small dc imbalance would also work. Which kind of makes an output transformer on the DAC redundant. How is the rest of your system configured.
In my system there were huge gains made by going to balanced. One of the big benefits of a transformer is that it allows you to get the full Dac output voltage while using a single ended signal chain.
@mbrennwa or other people with experience/knowledge of the Sowter 9335 transformers 
I would soon like to try my 9335 transformers but I have absolutely no prior experiences in this field, so a couple of questions...please!!!
I will only use the 9335 as simple single ended output transformers and not as TVC for now...Maybe later... The DDDac is a Quad-decker. Preamps input impedance is 100K.
1. Is it as simple as connecting the red and white/orange wires to the POS and NEG pads (Primary side) and the gray and blue/yellow wires to the RCA-connectors (Secondary side)? The Gray to the shield/chassis.
2. On the diagram for the 9335 on Sowters site there seems to be a resistor connecting the secondary wires. A Secondary-side IV-resistor? The DDDac diagrams doesn't show this resistor. Should I use this resistor in my scenario and if yes... what value?
3. There are 25 other, at this point, unused wires coming out of the transformers with non-insulated ends. Some of these might touch each other. Should I make sure this doesn't happen or is it of no consequences?
Thank you very much...
Regards
Martin Roerup
I would soon like to try my 9335 transformers but I have absolutely no prior experiences in this field, so a couple of questions...please!!!
I will only use the 9335 as simple single ended output transformers and not as TVC for now...Maybe later... The DDDac is a Quad-decker. Preamps input impedance is 100K.
1. Is it as simple as connecting the red and white/orange wires to the POS and NEG pads (Primary side) and the gray and blue/yellow wires to the RCA-connectors (Secondary side)? The Gray to the shield/chassis.
2. On the diagram for the 9335 on Sowters site there seems to be a resistor connecting the secondary wires. A Secondary-side IV-resistor? The DDDac diagrams doesn't show this resistor. Should I use this resistor in my scenario and if yes... what value?
3. There are 25 other, at this point, unused wires coming out of the transformers with non-insulated ends. Some of these might touch each other. Should I make sure this doesn't happen or is it of no consequences?
Thank you very much...
Regards
Martin Roerup
@mbrennwa or other people with experience/knowledge of the Sowter 9335 transformers
I would soon like to try my 9335 transformers but I have absolutely no prior experiences in this field, so a couple of questions...please!!!
I will only use the 9335 as simple single ended output transformers and not as TVC for now...Maybe later... The DDDac is a Quad-decker. Preamps input impedance is 100K.
1. Is it as simple as connecting the red and white/orange wires to the POS and NEG pads (Primary side) and the gray and blue/yellow wires to the RCA-connectors (Secondary side)? The Gray to the shield/chassis.
2. On the diagram for the 9335 on Sowters site there seems to be a resistor connecting the secondary wires. A Secondary-side IV-resistor? The DDDac diagrams doesn't show this resistor. Should I use this resistor in my scenario and if yes... what value?
3. There are 25 other, at this point, unused wires coming out of the transformers with non-insulated ends. Some of these might touch each other. Should I make sure this doesn't happen or is it of no consequences?
Thank you very much...
Regards
Martin Roerup
Hi,
For 1, those are the correct wires to use all coming from the clear sleeve on the TVC.
For 2, I don’t think you need this resistor with an amp input impedance of 100K. I don’t use one though I am using balanced monoblocka with 200k impedance.
For 3, do not let the wires connect to each other else they will short out parts of the secondary windings which will give some strange output results.
—kurand
Hi guys, as everything sounds great and is working well here I think it's time for further improvement
So I want to get the influence of the format conversion and time alignment from the logic of the main board out of the equation. I was thinking of the following:
First I want the right-justified signal reclocked (rather then the i2s and then converting after reclocking) so I would either have to put the reclocker after the shift registers of the main board or ditch the logic for the analog conversion completely and get the pi to output right-justified instead of i2s format, should be doable with the newer kernels and is my preferred option. In both cases i would need to alter LRCK or Data to get both, left and right channel output.
It says here on the dddac website:
But if you don't shift the LRCK the 32 bits with the Data line wouldn't that mean that the data for one channel now refers to the other one (e.g.right is now played on the left, not that it would matter, just for understanding). I guess that this didn't happen in doedes circuit because i2s and right-justified have inverted LRCK's. So pretty nifty actually that you get alignement and proper word selection with one 32bit shift
I think what Doede means with "alignment that's probably not audible" is that the right and left channel data get interpreted alternately instead of at the same time if there were no change in LRCK. Perhaps someone can tell me if this is right.
So when I don't need to shift the data signal because I (presumably) already have a right-justified format I should be able to get the left right separation by shifting the Wordclock (LRCK) 32bit instead, right?
An alternative would be to use a differential clock buffer and output one normal and one inverted LRCK though I'm not 100% this works with the 1794a in external filter mode, perhaps someone can help me out here
I want to do this because I assume that jitter and distortion on LRCK is not quite as influential as on the data or clock (BCK) signal. Also it seems cleaner to have less parts between the reclocker and the DAC-chips.
Perhaps someone here has already tried something like this or can give me some tips before I get the parts, a recommendation if I should use time shifting or inverting on the LRCK would be helpful.
Greetings Oli
PS: No late night sessions, I promise ;D
So I want to get the influence of the format conversion and time alignment from the logic of the main board out of the equation. I was thinking of the following:
First I want the right-justified signal reclocked (rather then the i2s and then converting after reclocking) so I would either have to put the reclocker after the shift registers of the main board or ditch the logic for the analog conversion completely and get the pi to output right-justified instead of i2s format, should be doable with the newer kernels and is my preferred option. In both cases i would need to alter LRCK or Data to get both, left and right channel output.
It says here on the dddac website:
But if you don't shift the LRCK the 32 bits with the Data line wouldn't that mean that the data for one channel now refers to the other one (e.g.right is now played on the left, not that it would matter, just for understanding). I guess that this didn't happen in doedes circuit because i2s and right-justified have inverted LRCK's. So pretty nifty actually that you get alignement and proper word selection with one 32bit shift
I think what Doede means with "alignment that's probably not audible" is that the right and left channel data get interpreted alternately instead of at the same time if there were no change in LRCK. Perhaps someone can tell me if this is right.
So when I don't need to shift the data signal because I (presumably) already have a right-justified format I should be able to get the left right separation by shifting the Wordclock (LRCK) 32bit instead, right?
An alternative would be to use a differential clock buffer and output one normal and one inverted LRCK though I'm not 100% this works with the 1794a in external filter mode, perhaps someone can help me out here
I want to do this because I assume that jitter and distortion on LRCK is not quite as influential as on the data or clock (BCK) signal. Also it seems cleaner to have less parts between the reclocker and the DAC-chips.
Perhaps someone here has already tried something like this or can give me some tips before I get the parts, a recommendation if I should use time shifting or inverting on the LRCK would be helpful.
Greetings Oli
PS: No late night sessions, I promise ;D
I have no clue about the PCM1704 but with the PCM1794a you can not use the channel select (right, left) in "NOS mode" so you need to differ the signal (BCK or LRCK) for one channel. My guess would be that if you deliver both sides with the same signal, they will play/do the same so you end up with two times the right or two times left channel, in DDDACs case probably two times left channel as this is the shifted one here.
So even if you can shift the 32 bits in the software domain, which (if possible) is probably more difficult to do than changing from i2s-standard to right-justified, you would need to shift it back for one side
So even if you can shift the 32 bits in the software domain, which (if possible) is probably more difficult to do than changing from i2s-standard to right-justified, you would need to shift it back for one side
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Uhm, the tricks done by the logic circuitry on the DDDAC board between I2S input and DAC chips are beyond me... but it would be cool if the RPi could be convinced to do it in software. Then the DDDAC logic circuitry could be skipped, and the reclocker could feed directly into the DAC chips.
As I said, almost directly. I think something like this could work:
I'm about to make a PCB for a right justified input mainboard. I will post it before I order though.
And yeah the logic circuitry is tricky, perhaps someone can fill me in on my (hopefully) last piece of the puzzle there:
Why is it that the half clock cycle delay caused by the shift registers is fixed by another shift of a half clock cycle on the same signal (data) rather then shifting the other two back (lrclk, bclk) to get them in sync again Oo
At the moment it looks like the data schould be a whole cycle late when it reaches the DAC modules. I mean it's great that it works but I don't know why and it makes me a bit ( ;D ) unsure in my inverter concept :/
greetings
edit: spelling
I'm about to make a PCB for a right justified input mainboard. I will post it before I order though.
And yeah the logic circuitry is tricky, perhaps someone can fill me in on my (hopefully) last piece of the puzzle there:
Why is it that the half clock cycle delay caused by the shift registers is fixed by another shift of a half clock cycle on the same signal (data) rather then shifting the other two back (lrclk, bclk) to get them in sync again Oo
At the moment it looks like the data schould be a whole cycle late when it reaches the DAC modules. I mean it's great that it works but I don't know why and it makes me a bit ( ;D ) unsure in my inverter concept :/
greetings
edit: spelling
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Hi guys, I'm not here much these days, but I saw that you are looking at running right justified data directly into the dac deck, so I wanted to post and say that yes this works and indeed works very nicely I have had my DDDAC running like this for around 4 years now!
I am very rusty on the details, but I can help to point you in the right direction maybe. I wrote some notes at the time, so maybe some if it is outdated, but I can post it up if you like?
Basically I have used a Beaglebone Black board and Miero's Botic driver to output 2 channels of right justified data. This goes via the Twisted Pear BBB Hermes Isolator Board and reclocked by the Cronus board, then wired it directly really close to the 1794 dac chips.
The advantage of the BBB hardware and Botic driver over a rpi solution is that it's easy to config it to spit out 2 channels of data in the right format (if you know the right settings). I'm happy to share the settings if that's helpful
I have had my DDDAC running like this for around 4 years now! I am very rusty on the details, but I can help to point you in the right direction maybe. I wrote some notes at the time, so maybe some if it is outdated, but I can post it up if you like?
Basically I have used a Beaglebone Black board and Miero's Botic driver to output 2 channels of right justified data. This goes via the Twisted Pear BBB Hermes Isolator Board and reclocked by the Cronus board, then wired it directly really close to the 1794 dac chips.
The advantage of the BBB hardware and Botic driver over a rpi solution is that it's easy to config it to spit out 2 channels of data in the right format (if you know the right settings). I'm happy to share the settings if that's helpful
Some days ago I swapped the LF50 for a NewClassD Regulator, DX7805 +5V UWB2 MK 2.
After a couple of days, I can say it is only improvement and no drawbacks. I have tried the LDOVR reg before, and with them, the DDDAC sounds worse to me.
Highly recommended.
4 deck Tent with regular psu and WaveIo + Sowters.
After a couple of days, I can say it is only improvement and no drawbacks. I have tried the LDOVR reg before, and with them, the DDDAC sounds worse to me.
Highly recommended.
4 deck Tent with regular psu and WaveIo + Sowters.
@dwjames, good to know that it works nicely I want to stick with the pi so no need to dig out code or something like that for the BBB (at least not for me ^^), but I'm curious about your setup. What is your output from the BBB? Do you have two different LRCLK or two different Data lines? Do you reclock 4 signals in the Cronus or do you reclock left and right on separate boards?
Greetings Oli
I want to stick with the pi so no need to dig out code or something like that for the BBB (at least not for me ^^), but I'm curious about your setup. What is your output from the BBB? Do you have two different LRCLK or two different Data lines? Do you reclock 4 signals in the Cronus or do you reclock left and right on separate boards?Greetings Oli
@dwjames, good to know that it works nicely
Greetings Oli
Hi Oli, I like to suggest you do the figuring-out and design work at the back ground and post the results? There will be many other stones on the road and the thread is not meant for a step by step and trial and error design project.
Or alternatively, make a new thread of it?