If the minimum impedance (or near it) occurs over a significant bandwidth and thus becomes the significant load for the time being considered then I would design for the minimum impedance. If wide phase angles also co-incided with that minimum impedance then I would design for the combination of low impedance and high phase angle. If the highest phase angles only applied when the impedance was well above minimum, then it seems that this new loading becomes a second operational condition to consider.Fanuc said:OK as a design example, what if I wanted to drive a loudspeaker that went down to 2 ohms. (monkey box)
Quad ELS57, Logans & Magneplaner Ribbons and some others will drop very low at HF, but these are mostly exceptions to the rule. Most moving coil speakers will do this at LF. <500Hz.
If I wanted a amp to drive 2 ohms continoius into a moderately reactively load, what sort of load phase angle should one look for ?
30 degrees, 45 or even 60 degress.
Advice welcome
Kevin
You may want to look at a series of these combinations and then pick the few that stress the output stage most severely.
low impedance at very high frequency (whether combined with high phase angle or not) will come in very short bursts (=real transients) and although they may repeat an extreme number of times each individual peak is very short. This is where I would look at 10uS peaks and use the 100uS current limit for that device/temp (if I had a speaker like that).
I take the easier route. I drive each half of the crossover with it's own amplifier. Bandwidth (and combinations likewise) to be considered is much reduced.
janneman said:
True, but only if the case is at 25 deg. in the first place.
It is conceptually analogous to Ohm's Law: Current~Power dissipated, Voltage~Temp., Resistance~Thermal resistance.
This is the basis for my example and, somewhat less obviously, your analysis below.
janneman said:
Right.
Hi all
some simple maths can be used to calculate phase angles and power.
Suppose we have a load impedance consisting of a series reactance z and resistance R. The current flow is V/(R+z). Get rid of the "j" in the denominator by multiplying by conjugate gives
i=V(R-z)/(R*R+z*z)
which gives the power in the load as the real term V*V*R/(R*R+z*z).
The phase angle is tan-1(z/R)
The power dissipated by the power transistors is simply the power supplied by the PSU minus the real power in the load as above. The power into the amplifier is Vcc*Iav, which does not care about phase angles as the average current is just the average current, whatever. Use the magnitude of the load [zeff=sqrt(R*R+z*z)]
to give the current and take sine-average Ipk*2/pi
In practice this means for a pure reactance the power trannys have to dissipate the full monty. Not a pretty sight when one supposes that the reactance dissipates nothing!
You have to consider the power dissipation as a function of frequency to calculate the worst case because z is frequency dependent. Having got the total power, the power per transistor can be calculated as an average for the frequency in question, giving a "power pulse" equivalent which you can use for heatsink calculations.
cheers
John
some simple maths can be used to calculate phase angles and power.
Suppose we have a load impedance consisting of a series reactance z and resistance R. The current flow is V/(R+z). Get rid of the "j" in the denominator by multiplying by conjugate gives
i=V(R-z)/(R*R+z*z)
which gives the power in the load as the real term V*V*R/(R*R+z*z).
The phase angle is tan-1(z/R)
The power dissipated by the power transistors is simply the power supplied by the PSU minus the real power in the load as above. The power into the amplifier is Vcc*Iav, which does not care about phase angles as the average current is just the average current, whatever. Use the magnitude of the load [zeff=sqrt(R*R+z*z)]
to give the current and take sine-average Ipk*2/pi
In practice this means for a pure reactance the power trannys have to dissipate the full monty. Not a pretty sight when one supposes that the reactance dissipates nothing!
You have to consider the power dissipation as a function of frequency to calculate the worst case because z is frequency dependent. Having got the total power, the power per transistor can be calculated as an average for the frequency in question, giving a "power pulse" equivalent which you can use for heatsink calculations.
cheers
John
john_ellis said:
Where have you been John ?
A dissection of Bob Cordell's compensation schema would be most welcome. Lag over the drains of the jfet LTP, but does it improve HF THD with respect to the output stage? . Output stage error correction is ignored for the time being.
Also, dual pole on the lag of PLIL. Enticing.....
I asked you this as you seem pretty sharp!. It isn't a competition or anything but just wanted to know your views....
http://www.diyaudio.com/forums/showthread.php?postid=1160755#post1160755
Post 764 on the BJT vs. MOSFET thread.
Look forward to your response.
Kevin
Massachusetts
My first visit to the USA was indeed Boston, Massachusetts. The so-called third largest shipping dock of the British Empire. Had a good look around harvard and much more importantly MIT.
MIT wins for me, harvard scholars are too into law, when scientists where defying gravity and putting a man on the moon at 18,000mph....
Cultures are different no doubt. Do like USA though.
Now that is a different phase angle to a reactive load.
My first visit to the USA was indeed Boston, Massachusetts. The so-called third largest shipping dock of the British Empire. Had a good look around harvard and much more importantly MIT.
MIT wins for me, harvard scholars are too into law, when scientists where defying gravity and putting a man on the moon at 18,000mph....
Cultures are different no doubt. Do like USA though.
Now that is a different phase angle to a reactive load.
Hi Mikeks
Otala proposed, way back in 1973 in his (in)famous paper, to use input phase lag and phase lead compensation.
I used the term PLIL to describe an approach where Otala's recommendations were used, but instead of using local feedback, with conventional global feedback. There is nothing wrong with Otala's original recommendations. Only thing he got wrong it seems is the need for local feedback. Distortion with global nfb can be made a lot lower.
cheers
John
Otala proposed, way back in 1973 in his (in)famous paper, to use input phase lag and phase lead compensation.
I used the term PLIL to describe an approach where Otala's recommendations were used, but instead of using local feedback, with conventional global feedback. There is nothing wrong with Otala's original recommendations. Only thing he got wrong it seems is the need for local feedback. Distortion with global nfb can be made a lot lower.
cheers
John
monkey box?
how about a real PA bass cabinet or a musician pairing a couple of 4 ohm Ampeg bass cabinets..... i wouldn't exactly call these applications "monkey boxes"......
ahhh..... i think i just got it...... subwoofer boxes with the small round ports that one can reach into, but not remove one's hand if grasping something that fell into the box?...... actually i have repaired a few of these that had mice go into and gnaw the spider wires on the woofer, or the tasty insulation on the internal wiring....... i'm trying to come up with a way to keep mice out of these ports.... maybe a wad of fiberglass stuffed into the port???????
how about a real PA bass cabinet or a musician pairing a couple of 4 ohm Ampeg bass cabinets..... i wouldn't exactly call these applications "monkey boxes"......
ahhh..... i think i just got it...... subwoofer boxes with the small round ports that one can reach into, but not remove one's hand if grasping something that fell into the box?...... actually i have repaired a few of these that had mice go into and gnaw the spider wires on the woofer, or the tasty insulation on the internal wiring....... i'm trying to come up with a way to keep mice out of these ports.... maybe a wad of fiberglass stuffed into the port???????
Mike et al,
Can I backtrack here.
I don’t have a problem with finding the derated POWER. I’m querying how it should be translated into graphical form, to provide the protection locus envelope.
If derated power/rated power = k, then I can draw two graphs which demonstrate that power i.e. P=kVce*Ic, or P = Vce*kIc. These are shown on my linear graph attached.
So, which is the one that should be used, and why. Some suggest the latter; Bensen used the former, from which I took mine.
Note that the worst case scenario is when Vce is derated. The curve is depressed to a greater extent at the critical Vcc< Vce<2*Vcc region. So, in the absence of definitive evidence, might it not be prudent to use that?
On another note, presumably R1+R2a (Mike’s) or R68? (Leach doesn’t show this) is used as the transient protection resistor value for the time constant?
Regards,
Brian.
Can I backtrack here.
I don’t have a problem with finding the derated POWER. I’m querying how it should be translated into graphical form, to provide the protection locus envelope.
If derated power/rated power = k, then I can draw two graphs which demonstrate that power i.e. P=kVce*Ic, or P = Vce*kIc. These are shown on my linear graph attached.
So, which is the one that should be used, and why. Some suggest the latter; Bensen used the former, from which I took mine.
Note that the worst case scenario is when Vce is derated. The curve is depressed to a greater extent at the critical Vcc< Vce<2*Vcc region. So, in the absence of definitive evidence, might it not be prudent to use that?
On another note, presumably R1+R2a (Mike’s) or R68? (Leach doesn’t show this) is used as the transient protection resistor value for the time constant?
Regards,
Brian.
Brian
Agree with Andrew T.
From what I read in the data sheets, the second breakdown locus holds virtually constant, but the temperature derating in the left hand (low Vce) side of the graph alters (moving downward with increasing temp). I believe this is because the second breakdown effects are driven by a high temperature, and are abnormally high. Chip temperature is normally lower, but at high temperatures on the chip, the power derating may be lower than Isb derating.
So using kIc for the derated power does this.
cheers
John
Agree with Andrew T.
From what I read in the data sheets, the second breakdown locus holds virtually constant, but the temperature derating in the left hand (low Vce) side of the graph alters (moving downward with increasing temp). I believe this is because the second breakdown effects are driven by a high temperature, and are abnormally high. Chip temperature is normally lower, but at high temperatures on the chip, the power derating may be lower than Isb derating.
So using kIc for the derated power does this.
cheers
John
Pingrs said:
Elementary my dear Watson:
Take this example.
The maximum permissible dissipation, assuming your heat sink maintains a transistor case temperature of 70 deg. C, is 128W.
Merely divide the later by Ic (or Vce) on your graph and obtain the corresponding Vce (or Ic); repeat several times.
The resulting hyperbola drawn through the points thus calculated is your new derated power limit.
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