This is a bad idea. The transistors need to be closely thermally coupled because temperature differences between them bring them closer to current hogging. Making them physically as close as possible is the best way to do this. Unfortunately this is not efficient usage of the surface of the heatsink.
An improvement might be to remove the heatsink fins between the two transistors so that they don't reduce thermal coupling. Although you would lose some cooling this way.
The danger of current hogging is something that can be calculated. It is conceivable that one might spread transistors out across a heatsink to improve cooling ability, only to be limited by current hogging because of the reduced thermal coupling between parallel BJTs. So there is a lot of thought involved if you want to push the limits of what is generally considered safe.
I have been reluctant to comment on this but you haven't had much response so here's my ideas.
First, the current mirror helper transistors seems undesirable. They add an extra pole and are usually detrimental to stability.
Bob adds them on p139 with the intention to improve the balance of the current mirror and match the potential drop of the EF assisted VAS.
Since you don't have an EF assisted VAS they offer no benefit in this circuit, only the stability downside and of course a little extra unneeded complexity.
Second, the LTP cascodes also seem undesirable. You have lowered the impedance into which the cascodes work with the 47K shunt resistor, which more or less defeats their purpose. And of course more complexity.
I did some simulations with Bob's resistor shunt solution and found it was not very robust to minor mismatches in LTP emitter resistor mismatch or transistor mismatch. It has no way to discriminate between Common Mode and Differential mode.
Hope that doesn't sound too critical, it's one of the few circuits in the book that I think needs to be re-examined.
Your circuit has cascodes on the VAS rather than EF assisted VAS so it should be less vulnerable, but I would recommend you try different sorts of mismatches and see how it balances.
You can use the spare transistors from the previous two comments to make a Common Mode Control Loop.
Or perhaps try Edmond Stuart's SuperTIS front end.
I also think your compensation may be vulnerable to component mismatch.
Bob does discuss this in his book and I think you should check this too.
I think a MIC works better for this application.
Actually I think it works better for most applications, but that's a different debate.
Best wishes
David
Hi Dave, glad you dropped by with good advice. I started and then put away this amp project 1.5 years ago disappointing at the VAS standing current. You gave good advice in that thread back then. I had a beta enhanced VAS in the beginning, you warned about the sensitivity and recommended a cascode VAS.
Dave, I have since found I needed to keep that "helper" transistor at the current mirror, and have it to pass a current about the same as VAS standing current, despite the unwanted pole. The helper transistors puts the base of VAS transistor at a little more than 2x Vbe off the rail, allowing a rather heavy VAS (DC) degeneration, it also helps narrow down the VAS standing current spread against Vbe mismatch within IPS to a manageable range, at least so in the simulation.
The LTP cascode transistors were there to help share the power dissipation. The tiny dual transistors used in LTP input are nowhere near the TO92 power handling capabilities, and the rails are +/-63v.
I'll probably eventually build Edmond Stuart's SuperTIS.
Hi Nattawa
I was looking at your photo again for quite a few minutes. I even looking for SMD MOSFET for the SS Relay. Looks like you are using two MOSFET like what I did to half the on resistance of the relay. I have been thinking about retry the layout with transistors on opposite side.
I really gave a lot of thoughts on the layout. I gave up the layout like yours because I insist on having a ground plane AND I don't want to have ground plane under the output plane. I don't want to add hundreds of pF capacitance from the output to ground. Also, I don't want to have ground plane under the driver traces to the output transistors for the same reason. I cannot do it with placement like yours. The only thing I can think of is using a ladder shape ground plane, that is a few "H" tied together horizontally. This, I can have full ground plane on each side with the power transistors. Then I have holes on the ground plane in the middle of the board where the output plane and the driving traces passing through to cut the capacitance by more than half.
I thought you said you want to fit into 10" X 6". You have a big heatsink, bigger than I expected. I would have spaced the transistor out if I were you. BUT, even now, you still have 5 pairs and you have the pcb already. But you still have a hefty heatsink. I won't do any cutting into the heatsink as it's part of the chassis that is very expensive.
I cannot give advice on the thermal issue as I need help also. But 46W does not sound that bad even though you have not optimize it. But I'll leave this to others that are more experienced. Just saying 46W does not alarm me.
Can you tell me what MOSFET you use for the SS relay?
Also, can you post the schematic of your design. I am curious in what you are talking about the VAS problem. I was not here 1.5years ago.
Thanks
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I think you have a good point there.
I only thought about this in a rudimentary way. Aluminum has a thermal conductivity of 205w/m/K. The heat sink I'm using has a base plate cross section of 0.01x0.15 m^2 (base height x heatsink length), and transistors are spaced at 0.022m along the width of the heat sink. Assume no other heat transfer present, a quick calculation shows it would take 14W net heat flow to cause a 1-degC temperature differential in between two pairs of transistors over 22mm distance. That seems to be a substantial amount of net heat flow per pair of transistors. In a real world things are much more complicated but perhaps that 14W net heat flow perhaps can still tell a little bit about what the metal base plate can do.
Yes, IS is the correct parameter to step in order to alter Vbe. Doubling IS will change Vbe by about 18mV.
In your circuit, I do not recommend using the helpered current mirror (i.e., Darlinton EF driving the mirror bases) approach with a 1T VAS. With a 2T VAS and a helpered current mirror, both current mirror transistors have a healthy 1Vbe of voltage for their Vcb.
It is always wise to do a sensitivity analysis for this circuit approach, where a differential bridging resistor is used on each pair of current mirror transistors to establish VAS standing current (i.e., a fix for the approach used by Slone). Vbe mismatch and resistor tolerances should be checked for their effect on VAS standing current. Of course, all emitter resistors in the LTPs and current mirrors should be 1% tolerance. It is desirable that VAS standing current be at least within +/-25%.
The value of the bridging resistors can be as low as necessary to achieve desired VAS standing current stability. Many complementary IPS amp designs do not use a current mirror and instead just use a load resistor. That arrangement also is subject to VAS standing current tolerances, but also suffers lower gain. The helpered current mirror with the bridging resistor allows the introduction of a current mirror and the achievement of higher gain, even when a much smaller value than 47k is used for the bridging resistance.
In another post a stability concern was raised about the use of a helpered current mirror itself. The helpered current mirror is widely used in linear integrated circuits, and is usually quite stable. However, I have seen some situations where its interaction with the subsequent Miller-compensated 2T VAS can cause some peaking in the open-loop response, usually above 10MHz, that can be indicative of smaller-than-desired stability margins. In cases like this, I have usually reduced the bias current in the helper and added a base-emitter capacitor to the helper, degrading its ft and in principle taking out the helper action at very high frequencies. At very high frequencies, ac-wise it just devolves into a non-helpered current mirror. All of the advantages of the helpered current mirror are retained in the audio band.
Cheers,
Bob
Alan, personally I would not use ground planes in an audio power amp. Some would argue it would be the best approach of getting a minimum power-load-return loop area, i.e. least loop inductance, because you do the loop around the 1.6mm PCB thickness. However in reality one can place the loop on one side of PCB and have a 0.8mm or 0.5mm gap between traces, and that means a lot smaller loop inductance. If needed, double up the traces on the other side of PCB to enhance current carrying capacity. Power/ground plane flooding also usually needs a lot of care in where they should go and should not go.
The MOSFET in the SS relay on my board is Infineon IPT059N15N3.
The original amp circuit can be found if you search the forum for "meistersinger amp".
Thanks
I looked at your schematic, are you referring to the VAS current problem due to the current mirror load of the complementary LTP IPS. I post the potential problem with Mr. Cordell in this thread about the problem with the 47K resistor trying to set the current.
Because the loop gain runs out at high frequency. Not enough gain to keep the distortion down.
If I understand correctly, gmphadte was commenting on a situation where a driver transistor was reacting too quickly to heatsink temperature changes brought on by a neighboring OPT, not on OPT-OPT imbalance.
I am very interested in your experience. First, how many parallel stages do you have when you use 0.1ohm emitter resistor?
Also, when you lower the resistance to 0.1ohm, did you increase the bias current to keep 26mV across the 0.1ohm to satisfy Oliver's condition?
So far, everyone here encourage me to use 0.22ohm minimum because I have 5 stages. I have no experience in any of this, I can only theorized that you can run higher current with lower resistance and meet the Oliver's condition with much higher bias current to get a larger class A region.
I really like to hear from you.
Thanks
I share your experience that it is useful to push the VAS transistor base away from the rail and increase the VAS emitter resistor.
But I have found it better to omit the helper transistor and instead keep the balance with increased emitter resistors in the current mirror.
This is win/win, the pole is eliminated and the increased CM resistors have lower noise (kind of counter-intuitive but documented and true)
OK, that's a sensible reason.
Would it make sense to just use a resistor here?
Thanks for the appreciative words.
Best wishes
David
Hi Bob
That "other post" was mine so I would like to discuss this.
I suspect that part of the reason that helpered Current Mirrors are used in ICs is specific to IC trade-offs where accurate, stable resistors are more difficult and "expensive" than transistors.
For a DIY PCB amplifier it's the reverse.
In my simulations the better way to match VAS and CM potentials has been with increased CM emitter resistors, that would be less desirable on an IC.
The stability improvement is not vast but it does help.
The noise is lower too, a personal concern of mine because I have an active system with directly connected compression drivers.
The resistors are already on the PCB, to increase the value a little is a simpler, more compact layout, a few less parts to solder or fail, and minutely cheaper than an extra transistor or two.
Best wishes
David
Could helpered CM also have been partly a response to the lack of decent PNP transistors in early fabrication processes?
Not directly, but did the compromises have a consequence here?
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I've measured (or had measured) three scenario's.
-big 300mm X 300mm extrusion (<.2C/w) with the 5 pairs together.
= not bad at all , less than 1/2mv between pairs all the way to a hot heatsink .
Most likely Idles @ 35C with 65ma bias
-smaller 140mm X 285mm - .4C/W (mine - slewmaster V2) 5 close pairs.
= up to 3 mv more at the center pairs when driven to >50C.
At idle, ends of extrusion were 36C , center was 43C.
- new 140 X 305mm - .4C/W , 5 pairs with equal area across the 300mm.
Would equal - 3 pair MT-200s spread to 225mm across another 140 X 305mm.
= less than .1mv between the 3 pair sanken @ 100ma , some pairs even "trade"
the higher bias as you race towards 50C+ (still stay .1mv).
so , not too much space ... but give each pair it own (equal) section of the
extrusion. Main Vbe is between pair 1 and 2 , so it get's an "average"
of 2 pairs . Separate driver Vbe is the "fast" player , the main just
has to set the "average" for the driver vbe to "pivot" on.
Had 200 days to get this right in the real world. 0C -50C rock solid.
Edit - strange that some say allow the OPS to stabilize. I set 65ma ,
I'm there in <60 seconds - @ 20C , still there at 50C , when I "crank it up" (play loudly).
OS
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Hi Dave,
I pointed out that helpered current mirrors are widely used in linear ICs as an example that they do not generally have a stability problem. Although it is true that in earlier days the lateral PNPs used had terrible beta, I don't think that has anything to do with why helpered current mirrors are used now.
Your concern about having two transistors in a tight loop having potentially 180 degree phase shift in loop current gain is noted, but that is also essentially the same situation as when a 2T VAS has Miller compensation. The 3T cascoded VAS is where one begins to get into that kind of trouble, with 3 transistors in the loop. Nevertheless, it is always important to simulate and poke around for any signs of peaking that may suggest a stability problem.
I like significant degeneration in the current mirrors as well, since the current mirror itself can contribute as much noise as the LTP under some conditions. Some people may not realize this. My designs always come in with input-referred noise of 4-10 nV/rt Hz, which is excellent for a power amplifier.
As I pointed out, if you are concerned about the stability of the helpered current mirror, you can always put a capacitor from base to emitter of the helper transistor.
With the helpered current mirror and 2T VAS, I usually set the CM and VAS degeneration resistors so that the voltage drop across all of them is about the same. BTW, I virtually always choose 10:1 degeneration for my VAS, meaning that a 10mA VAS will have an emitter resistor of about 25 ohms.
There is another benefit to using the helpered CM and 2T VAS. This arrangement, when properly implemented, makes the voltages at the two CM collectors the same. This obviously makes possible the use of the differential load resistor. However, it also allows the use of paralleled clamping diodes that prevent the collectors from moving more than 1 Vbe away from nominal when clipping occurs. I have found this to provide cleaner clipping and also can play a role in limiting over-current in the EF transistor of the 2T VAS.
I will try to address this issue in more depth in my second edition.
Cheers,
Bob
It has lower thermal resistance and higher thermal inertia, but is expensive.
A heat spreader bar is a good way of maximizing thermal coupling between BJTs as well as reducing insulator thermal resistance. The transistors can be bolted directly to the bar with thermal paste, and the bar can be insulated from the heatsink with a large insulator. Thermal resistance will be lower because the bar itself will have more total surface area between it and the heatsink than the transistors would alone. The bar does not need to be much larger than the transistors, so would be less expensive than using a solid copper heatsink. And the near perfect interface from transistor tab to copper thermal mass will probably improve SOA.
Did I miss something?
Go fancy heatsink, combination of solid and foamed aluminum.
(e.g. Le Son power amp : http://static.wixstatic.com/media/a...pg_srb_p_940_440_75_22_0.50_1.20_0.00_jpg_srb )